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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id c21sm13316525wmb.46.2019.10.14.06.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2019 06:17:53 -0700 (PDT) Date: Mon, 14 Oct 2019 15:17:52 +0200 From: Thierry Reding To: Rob Herring Cc: JC Kuo , gregkh@linuxfoundation.org, jonathanh@nvidia.com, kishon@ti.com, linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, nkristam@nvidia.com Subject: Re: [PATCH v4 3/5] dt-bindings: phy: tegra: Add Tegra194 support Message-ID: <20191014131752.GF422231@ulmo> References: <20191009024343.30218-1-jckuo@nvidia.com> <20191009024343.30218-4-jckuo@nvidia.com> <20191009233900.GA9109@bogus> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="l+goss899txtYvYf" Content-Disposition: inline In-Reply-To: <20191009233900.GA9109@bogus> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org --l+goss899txtYvYf Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Oct 09, 2019 at 06:39:00PM -0500, Rob Herring wrote: > On Wed, Oct 09, 2019 at 10:43:41AM +0800, JC Kuo wrote: > > Extend the bindings to cover the set of features found in Tegra194. > > Note that, technically, there are four more supplies connected to the > > XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL) > > , but the power sequencing requirements of Tegra194 require these to be > > under the control of the PMIC. > >=20 > > Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it is > > possible for some platforms have long signal trace that could not > > provide sufficient electrical environment for Gen 2 speed. To deal with > > this, a new device node property "nvidia,disable-gen2" was added to > > Tegra194 that be used to specifically disable Gen 2 speed for a > > particular USB 3.0 port so that the port can be limited to Gen 1 speed > > and avoid the instability. >=20 > I suspect this may be a common issue and we should have a common=20 > property. Typically, this kind of property is in the controller though=20 > and supports multiple speed limits. See PCI bindings for inspiration. Given that support for gen 2 speeds is dependent on signal trace length, it doesn't really make sense to restrict the whole controller to a given speed if only the signal trace for a single port exceeds the limit for which gen 2 would work. Also, the USB PHYs are in a different hardware block than the USB controller, so this really is a property of the PHY block, not the USB controller. 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