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From: Peter Chen <peter.chen@kernel.org>
To: Pawel Laszczak <pawell@cadence.com>
Cc: linux-usb@vger.kernel.org
Subject: About use case of cdns3-pci-wrap.c
Date: Sat, 27 Mar 2021 12:50:16 +0800	[thread overview]
Message-ID: <20210327045016.GD28870@b29397-desktop> (raw)

Hi Pawel,

From the code of this file, it seems the controller driver is running at
PC side, but the hardware controller is at verification board, the two sides
are connected by PCIe. Am I right?

If I am right, the memory (eg, the TRB ring address and data buffer) the hardware
try to visit is at PC side, but how controller visits PC memory since the TRB ring
address is allocated dynamically by controller device driver running at
PC? How the local bus arbiter knows it is PCIe address at verification board?
Besides, could the upstream code run this IP verification solution through PCIe
without changing any code?

Thanks.

-- 

Thanks,
Peter Chen


             reply	other threads:[~2021-03-27  4:51 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-27  4:50 Peter Chen [this message]
2021-03-30  3:57 ` About use case of cdns3-pci-wrap.c Pawel Laszczak

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