[PATCH v1 0/8] enable usb support on rk356x

[PATCH v1 0/8] enable usb support on rk356x

[Peter Geis]

Good Morning,

This is my patch series that I have maintained out of tree until the
combophy driver landed. Note, it is dependent on this series to function
(aside from the rk3566 dwc3-otg port, which will work currently).

This series is still dependent on Patch 4 of the combophy series, which
has yet to be accepted.

Patches 1 and 2 add the dt bindings for the grf changes necessary for
this series.
Patch 3 adds support to the grf driver to set the rk3566 otg clock
source.
Patch 4 is a downstream patch ported forward to shut down the usb3 clock
when the controller is operating in usb2 mode.
Patches 5 and 6 clean up the dwc3-of-simple driver and add the
compatible for the rk3568.
Patch 7 adds the dwc3 nodes to the rk356x device tree includes.
Patch 8 enables the dwc3 nodes on the Quartz64 Model A.

Please review and apply.

Very Respectfully,
Peter Geis

Bin Yang (1):
  usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode

Peter Geis (7):
  dt-bindings: soc: grf: add rk3566-pipe-grf compatible
  dt-bindings: usb: dwc3: add description for rk3568
  soc: rockchip: set dwc3 clock for rk3566
  usb: dwc3: reorder dwc-of-simple compatibles
  usb: dwc3: add rk3568 dwc3 support
  arm64: dts: rockchip: add the dwc3 usb3 nodes to rk356x
  arm64: dts: rockchip: enable the dwc3 nodes on quartz64-a

 .../devicetree/bindings/soc/rockchip/grf.yaml |  1 +
 .../bindings/usb/rockchip,dwc3.yaml           |  7 ++-
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 37 +++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3566.dtsi      | 12 +++++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  9 ++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 45 ++++++++++++++++++-
 drivers/soc/rockchip/grf.c                    | 17 +++++++
 drivers/usb/dwc3/core.c                       |  4 ++
 drivers/usb/dwc3/core.h                       |  1 +
 drivers/usb/dwc3/dwc3-of-simple.c             | 10 +++--
 10 files changed, 137 insertions(+), 6 deletions(-)

-- 
2.25.1

[PATCH v1 2/8] dt-bindings: usb: dwc3: add description for rk3568

[Peter Geis]

The rk3568 dwc3 controllers are backwards compatible with the rk3399.
Add the device tree description for it.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
index 04077f2d7faf..e3044e81cc72 100644
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
@@ -30,6 +30,7 @@ select:
         enum:
           - rockchip,rk3328-dwc3
           - rockchip,rk3399-dwc3
+          - rockchip,rk3568-dwc3
   required:
     - compatible
 
@@ -39,6 +40,7 @@ properties:
       - enum:
           - rockchip,rk3328-dwc3
           - rockchip,rk3399-dwc3
+          - rockchip,rk3568-dwc3
       - const: snps,dwc3
 
   reg:
@@ -75,7 +77,10 @@ properties:
     maxItems: 1
 
   reset-names:
-    const: usb3-otg
+    items:
+      - enum:
+          - usb3-otg
+          - usb3-host
 
 unevaluatedProperties: false
 
-- 
2.25.1

[PATCH v1 4/8] usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode

[Peter Geis]

From: Bin Yang <yangbin@rock-chips.com>

In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.

Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 drivers/usb/dwc3/core.c | 4 ++++
 drivers/usb/dwc3/core.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 18adddfba3da..032d40794fae 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1167,6 +1167,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
 		if (dwc->parkmode_disable_ss_quirk)
 			reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
 
+		if (dwc->maximum_speed == USB_SPEED_HIGH ||
+		    dwc->maximum_speed == USB_SPEED_FULL)
+			reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
+
 		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 	}
 
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index eb9c1efced05..ea3ca04406bb 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -259,6 +259,7 @@
 /* Global User Control 1 Register */
 #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK	BIT(26)
 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW		BIT(24)
 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS		BIT(17)
 
-- 
2.25.1

[PATCH v1 5/8] usb: dwc3: reorder dwc-of-simple compatibles

[Peter Geis]

The dwc3-of-simple driver is getting rather disorganized with the new
inclusions.
Reorder the dwc3-of-simple compatibles to be alphabetical.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 drivers/usb/dwc3/dwc3-of-simple.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index 71fd620c5161..9dc6295df6b1 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -171,12 +171,12 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
 };
 
 static const struct of_device_id of_dwc3_simple_match[] = {
-	{ .compatible = "rockchip,rk3399-dwc3" },
-	{ .compatible = "cavium,octeon-7130-usb-uctl" },
-	{ .compatible = "sprd,sc9860-dwc3" },
 	{ .compatible = "allwinner,sun50i-h6-dwc3" },
+	{ .compatible = "cavium,octeon-7130-usb-uctl" },
 	{ .compatible = "hisilicon,hi3670-dwc3" },
 	{ .compatible = "intel,keembay-dwc3" },
+	{ .compatible = "rockchip,rk3399-dwc3" },
+	{ .compatible = "sprd,sc9860-dwc3" },
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
-- 
2.25.1

[PATCH v1 6/8] usb: dwc3: add rk3568 dwc3 support

[Peter Geis]

The rk3568 dwc3 controller is backwards compatible with the rk3399 dwc3
controller.
Add support for it to the dwc3-of-simple driver.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 drivers/usb/dwc3/dwc3-of-simple.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index 9dc6295df6b1..1d52a261af55 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -49,7 +49,8 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
 	 * Some controllers need to toggle the usb3-otg reset before trying to
 	 * initialize the PHY, otherwise the PHY times out.
 	 */
-	if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
+	if (of_device_is_compatible(np, "rockchip,rk3399-dwc3") |
+	    of_device_is_compatible(np, "rockchip,rk3568-dwc3"))
 		simple->need_reset = true;
 
 	simple->resets = of_reset_control_array_get(np, false, true,
@@ -176,6 +177,7 @@ static const struct of_device_id of_dwc3_simple_match[] = {
 	{ .compatible = "hisilicon,hi3670-dwc3" },
 	{ .compatible = "intel,keembay-dwc3" },
 	{ .compatible = "rockchip,rk3399-dwc3" },
+	{ .compatible = "rockchip,rk3568-dwc3" },
 	{ .compatible = "sprd,sc9860-dwc3" },
 	{ /* Sentinel */ }
 };
-- 
2.25.1

Re: [PATCH v1 2/8] dt-bindings: usb: dwc3: add description for rk3568

[Johan Jonker]

Hi Peter,

Lots of USB series all of a sudden.
Combine possible?

On 2/25/22 15:54, Peter Geis wrote:
> The rk3568 dwc3 controllers are backwards compatible with the rk3399.
> Add the device tree description for it.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> index 04077f2d7faf..e3044e81cc72 100644
> --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> @@ -30,6 +30,7 @@ select:
>          enum:
>            - rockchip,rk3328-dwc3
>            - rockchip,rk3399-dwc3
> +          - rockchip,rk3568-dwc3
>    required:
>      - compatible
>  
> @@ -39,6 +40,7 @@ properties:
>        - enum:
>            - rockchip,rk3328-dwc3
>            - rockchip,rk3399-dwc3
> +          - rockchip,rk3568-dwc3
>        - const: snps,dwc3
>  
>    reg:
> @@ -75,7 +77,10 @@ properties:
>      maxItems: 1
>  
he
>    reset-names:
> -    const: usb3-otg
> +    items:
> +      - enum:
> +          - usb3-otg
> +          - usb3-host

The use of reset-names is "sort of" only related to the rk3399 legacy
node. Still using this sub node DT to not to break older existing boot
loaders.

https://github.com/torvalds/linux/search?q=usb3-otg

It's only mentioned as comment in dwc3-of-simple.c but not used:

 	simple->resets = of_reset_control_array_get(np, false, true,
						    true);
core.c uses something similar.

	dwc->reset = devm_reset_control_array_get_optional_shared(dev);
	if (IS_ERR(dwc->reset))
		return PTR_ERR(dwc->reset);


Up to the maintainers, but I wouldn't add another variant/name for the
same thing as it also optional(= not required) and no longer needed.

Johan

===

Maybe drop PCLK_PIPE as well to reduce notifications.

See example:
https://lore.kernel.org/linux-rockchip/20220225131602.2283499-4-michael.riesch@wolfvision.net/T/#u

>  
>  unevaluatedProperties: false
>  

Re: [PATCH v1 6/8] usb: dwc3: add rk3568 dwc3 support

[Michael Riesch]

Hi Peter,

On 2/25/22 15:54, Peter Geis wrote:
> The rk3568 dwc3 controller is backwards compatible with the rk3399 dwc3
> controller.
> Add support for it to the dwc3-of-simple driver.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  drivers/usb/dwc3/dwc3-of-simple.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
> index 9dc6295df6b1..1d52a261af55 100644
> --- a/drivers/usb/dwc3/dwc3-of-simple.c
> +++ b/drivers/usb/dwc3/dwc3-of-simple.c
> @@ -49,7 +49,8 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
>  	 * Some controllers need to toggle the usb3-otg reset before trying to
>  	 * initialize the PHY, otherwise the PHY times out.
>  	 */
> -	if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
> +	if (of_device_is_compatible(np, "rockchip,rk3399-dwc3") |
> +	    of_device_is_compatible(np, "rockchip,rk3568-dwc3"))
>  		simple->need_reset = true;

Maybe read this value out the match data...

>  	simple->resets = of_reset_control_array_get(np, false, true,
> @@ -176,6 +177,7 @@ static const struct of_device_id of_dwc3_simple_match[] = {
>  	{ .compatible = "hisilicon,hi3670-dwc3" },
>  	{ .compatible = "intel,keembay-dwc3" },
>  	{ .compatible = "rockchip,rk3399-dwc3" },
> +	{ .compatible = "rockchip,rk3568-dwc3" },

... so all future variants that are compatible to the rk3399 can share it?

Best regards,
Michael

>  	{ .compatible = "sprd,sc9860-dwc3" },
>  	{ /* Sentinel */ }
>  };

Re: [PATCH v1 4/8] usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode

[Jack Pham]

+Thinh

Hi Peter,

On Fri, Feb 25, 2022 at 09:54:27AM -0500, Peter Geis wrote:
> From: Bin Yang <yangbin@rock-chips.com>
> 
> In the 3.0 device core, if the core is programmed to operate in
> 2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
> the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
> clock. Enabling this feature allows the pipe3 clock to be not-running
> when forcibly operating in 2.0 device mode.
> 
> Signed-off-by: Bin Yang <yangbin@rock-chips.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  drivers/usb/dwc3/core.c | 4 ++++
>  drivers/usb/dwc3/core.h | 1 +
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 18adddfba3da..032d40794fae 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -1167,6 +1167,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
>  		if (dwc->parkmode_disable_ss_quirk)
>  			reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
>  
> +		if (dwc->maximum_speed == USB_SPEED_HIGH ||
> +		    dwc->maximum_speed == USB_SPEED_FULL)
> +			reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
> +

I doubt this is applicable to all revisions of the DWC_usb3x IP cores?
For instance in the programming guide for DWC_usb31 1.90a bit 26 of
GUCTL1 is 'Reserved'.  While I do see it in the DWC_usb3 databook,
table 4-8 entry "Remove pipe_clk mux for 2.0 mode?" mentions this
feature was only added in v2.90a.

So this setting at least needs a revision check to make sure we're not
causing unexpected behavior.  Something like

	DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)

Jack

>  		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
>  	}
>  
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index eb9c1efced05..ea3ca04406bb 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -259,6 +259,7 @@
>  /* Global User Control 1 Register */
>  #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
>  #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
> +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK	BIT(26)
>  #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW		BIT(24)
>  #define DWC3_GUCTL1_PARKMODE_DISABLE_SS		BIT(17)
>  
> -- 
> 2.25.1
> 

Re: [PATCH v1 4/8] usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode

[Peter Geis]

On Fri, Feb 25, 2022 at 12:16 PM Jack Pham <quic_jackp@quicinc.com> wrote:
>
> +Thinh
>
> Hi Peter,
>
> On Fri, Feb 25, 2022 at 09:54:27AM -0500, Peter Geis wrote:
> > From: Bin Yang <yangbin@rock-chips.com>
> >
> > In the 3.0 device core, if the core is programmed to operate in
> > 2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
> > the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
> > clock. Enabling this feature allows the pipe3 clock to be not-running
> > when forcibly operating in 2.0 device mode.
> >
> > Signed-off-by: Bin Yang <yangbin@rock-chips.com>
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  drivers/usb/dwc3/core.c | 4 ++++
> >  drivers/usb/dwc3/core.h | 1 +
> >  2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 18adddfba3da..032d40794fae 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -1167,6 +1167,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
> >               if (dwc->parkmode_disable_ss_quirk)
> >                       reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
> >
> > +             if (dwc->maximum_speed == USB_SPEED_HIGH ||
> > +                 dwc->maximum_speed == USB_SPEED_FULL)
> > +                     reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
> > +
>
> I doubt this is applicable to all revisions of the DWC_usb3x IP cores?
> For instance in the programming guide for DWC_usb31 1.90a bit 26 of
> GUCTL1 is 'Reserved'.  While I do see it in the DWC_usb3 databook,
> table 4-8 entry "Remove pipe_clk mux for 2.0 mode?" mentions this
> feature was only added in v2.90a.

I was wondering about that, thanks for confirming for me.
Is it possible to get a copy of this programming guide or is it closed?

>
> So this setting at least needs a revision check to make sure we're not
> causing unexpected behavior.  Something like
>
>         DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)

Will do, I appreciate it.

>
> Jack
>
> >               dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
> >       }
> >
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > index eb9c1efced05..ea3ca04406bb 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -259,6 +259,7 @@
> >  /* Global User Control 1 Register */
> >  #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT    BIT(31)
> >  #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS   BIT(28)
> > +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK      BIT(26)
> >  #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW                BIT(24)
> >  #define DWC3_GUCTL1_PARKMODE_DISABLE_SS              BIT(17)
> >
> > --
> > 2.25.1
> >

Re: [PATCH v1 6/8] usb: dwc3: add rk3568 dwc3 support

[Peter Geis]

On Fri, Feb 25, 2022 at 12:08 PM Michael Riesch
<michael.riesch@wolfvision.net> wrote:
>
> Hi Peter,
>
> On 2/25/22 15:54, Peter Geis wrote:
> > The rk3568 dwc3 controller is backwards compatible with the rk3399 dwc3
> > controller.
> > Add support for it to the dwc3-of-simple driver.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  drivers/usb/dwc3/dwc3-of-simple.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
> > index 9dc6295df6b1..1d52a261af55 100644
> > --- a/drivers/usb/dwc3/dwc3-of-simple.c
> > +++ b/drivers/usb/dwc3/dwc3-of-simple.c
> > @@ -49,7 +49,8 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
> >        * Some controllers need to toggle the usb3-otg reset before trying to
> >        * initialize the PHY, otherwise the PHY times out.
> >        */
> > -     if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
> > +     if (of_device_is_compatible(np, "rockchip,rk3399-dwc3") |
> > +         of_device_is_compatible(np, "rockchip,rk3568-dwc3"))
> >               simple->need_reset = true;
>
> Maybe read this value out the match data...

This is a good idea, thanks!

>
> >       simple->resets = of_reset_control_array_get(np, false, true,
> > @@ -176,6 +177,7 @@ static const struct of_device_id of_dwc3_simple_match[] = {
> >       { .compatible = "hisilicon,hi3670-dwc3" },
> >       { .compatible = "intel,keembay-dwc3" },
> >       { .compatible = "rockchip,rk3399-dwc3" },
> > +     { .compatible = "rockchip,rk3568-dwc3" },
>
> ... so all future variants that are compatible to the rk3399 can share it?
>
> Best regards,
> Michael
>
> >       { .compatible = "sprd,sc9860-dwc3" },
> >       { /* Sentinel */ }
> >  };

Re: [PATCH v1 2/8] dt-bindings: usb: dwc3: add description for rk3568

[Peter Geis]

On Fri, Feb 25, 2022 at 11:07 AM Johan Jonker <jbx6244@gmail.com> wrote:
>
> Hi Peter,
>
> Lots of USB series all of a sudden.
> Combine possible?
>
> On 2/25/22 15:54, Peter Geis wrote:
> > The rk3568 dwc3 controllers are backwards compatible with the rk3399.
> > Add the device tree description for it.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> > index 04077f2d7faf..e3044e81cc72 100644
> > --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> > +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
> > @@ -30,6 +30,7 @@ select:
> >          enum:
> >            - rockchip,rk3328-dwc3
> >            - rockchip,rk3399-dwc3
> > +          - rockchip,rk3568-dwc3
> >    required:
> >      - compatible
> >
> > @@ -39,6 +40,7 @@ properties:
> >        - enum:
> >            - rockchip,rk3328-dwc3
> >            - rockchip,rk3399-dwc3
> > +          - rockchip,rk3568-dwc3
> >        - const: snps,dwc3
> >
> >    reg:
> > @@ -75,7 +77,10 @@ properties:
> >      maxItems: 1
> >
> he
> >    reset-names:
> > -    const: usb3-otg
> > +    items:
> > +      - enum:
> > +          - usb3-otg
> > +          - usb3-host
>
> The use of reset-names is "sort of" only related to the rk3399 legacy
> node. Still using this sub node DT to not to break older existing boot
> loaders.
>
> https://github.com/torvalds/linux/search?q=usb3-otg
>
> It's only mentioned as comment in dwc3-of-simple.c but not used:
>
>         simple->resets = of_reset_control_array_get(np, false, true,
>                                                     true);
> core.c uses something similar.
>
>         dwc->reset = devm_reset_control_array_get_optional_shared(dev);
>         if (IS_ERR(dwc->reset))
>                 return PTR_ERR(dwc->reset);
>
>
> Up to the maintainers, but I wouldn't add another variant/name for the
> same thing as it also optional(= not required) and no longer needed.

I left these named separately since they are different reset signals,
but if it isn't an issue I don't mind having them both be usb3-otg.

>
> Johan
>
> ===
>
> Maybe drop PCLK_PIPE as well to reduce notifications.

I'll be conducting testing to determine if we need PCLK_PIPE here, and
as long as it isn't working simply because it's enabled by someone
else I'll drop it.
Ideally, it would be nice to have a proper clock map for these chips,
but currently that's not in the TRM.

>
> See example:
> https://lore.kernel.org/linux-rockchip/20220225131602.2283499-4-michael.riesch@wolfvision.net/T/#u
>
> >
> >  unevaluatedProperties: false
> >

Thanks for the review!