Re: [PATCH v1 4/8] usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode

[Jack Pham <quic_jackp@quicinc.com>]

+Thinh

Hi Peter,

On Fri, Feb 25, 2022 at 09:54:27AM -0500, Peter Geis wrote:
> From: Bin Yang <yangbin@rock-chips.com>
> 
> In the 3.0 device core, if the core is programmed to operate in
> 2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
> the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
> clock. Enabling this feature allows the pipe3 clock to be not-running
> when forcibly operating in 2.0 device mode.
> 
> Signed-off-by: Bin Yang <yangbin@rock-chips.com>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  drivers/usb/dwc3/core.c | 4 ++++
>  drivers/usb/dwc3/core.h | 1 +
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 18adddfba3da..032d40794fae 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -1167,6 +1167,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
>  		if (dwc->parkmode_disable_ss_quirk)
>  			reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
>  
> +		if (dwc->maximum_speed == USB_SPEED_HIGH ||
> +		    dwc->maximum_speed == USB_SPEED_FULL)
> +			reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
> +

I doubt this is applicable to all revisions of the DWC_usb3x IP cores?
For instance in the programming guide for DWC_usb31 1.90a bit 26 of
GUCTL1 is 'Reserved'.  While I do see it in the DWC_usb3 databook,
table 4-8 entry "Remove pipe_clk mux for 2.0 mode?" mentions this
feature was only added in v2.90a.

So this setting at least needs a revision check to make sure we're not
causing unexpected behavior.  Something like

	DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)

Jack

>  		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
>  	}
>  
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index eb9c1efced05..ea3ca04406bb 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -259,6 +259,7 @@
>  /* Global User Control 1 Register */
>  #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
>  #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
> +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK	BIT(26)
>  #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW		BIT(24)
>  #define DWC3_GUCTL1_PARKMODE_DISABLE_SS		BIT(17)
>  
> -- 
> 2.25.1
>