From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Sanjay R Mehta <Sanju.Mehta@amd.com>
Cc: andreas.noever@gmail.com, michael.jamet@intel.com,
YehezkelShB@gmail.com, linux-usb@vger.kernel.org,
Sanath S <Sanath.S@amd.com>
Subject: Re: [PATCH Internal] thunderbolt: Remove enabling/disabling TMU based on CLx
Date: Wed, 21 Jun 2023 14:15:25 +0300 [thread overview]
Message-ID: <20230621111525.GL45886@black.fi.intel.com> (raw)
In-Reply-To: <1687343842-17881-1-git-send-email-Sanju.Mehta@amd.com>
On Wed, Jun 21, 2023 at 05:37:22AM -0500, Sanjay R Mehta wrote:
> From: Sanath S <Sanath.S@amd.com>
>
> Since TMU is enabled by default on Intel SOCs for USB4 before Alpine
> Ridge, explicit enabling or disabling of TMU is not required.
>
> However, the current implementation of enabling or disabling TMU based
> on CLx state is inadequate as not all SOCs with CLx disabled have TMU
> enabled by default, such as AMD Yellow Carp and Pink Sardine.
>
> To address this, a quirk named "QUIRK_TMU_DEFAULT_ENABLED" is
> implemented to skip the enabling or disabling of TMU for SOCs where it
> is already enabled by default, such as Intel SOCs prior to Alpine Ridge.
If it is enabled by default "enabling" it again should not be a problem.
Can you elaborate this more?
next prev parent reply other threads:[~2023-06-21 11:16 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 10:37 [PATCH Internal] thunderbolt: Remove enabling/disabling TMU based on CLx Sanjay R Mehta
2023-06-21 10:52 ` Greg KH
2023-06-21 10:52 ` Greg KH
2023-06-21 10:57 ` Sanjay R Mehta
2023-06-21 11:15 ` Mika Westerberg [this message]
2023-06-21 12:18 ` Sanjay R Mehta
2023-06-21 12:54 ` Mika Westerberg
2023-06-21 16:07 ` Sanjay R Mehta
2023-06-22 4:45 ` Mika Westerberg
2023-07-06 13:48 ` Sanjay R Mehta
2023-07-31 9:41 ` Mika Westerberg
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