From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54DFEEEB58F for ; Wed, 13 Sep 2023 04:35:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233016AbjIMEfC (ORCPT ); Wed, 13 Sep 2023 00:35:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229879AbjIMEfB (ORCPT ); Wed, 13 Sep 2023 00:35:01 -0400 X-Greylist: delayed 572 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 12 Sep 2023 21:34:56 PDT Received: from bmailout2.hostsharing.net (bmailout2.hostsharing.net [IPv6:2a01:37:3000::53df:4ef0:0]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB2F7AB; Tue, 12 Sep 2023 21:34:56 -0700 (PDT) Received: from h08.hostsharing.net (h08.hostsharing.net [IPv6:2a01:37:1000::53df:5f1c:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "*.hostsharing.net", Issuer "RapidSSL Global TLS RSA4096 SHA256 2022 CA1" (verified OK)) by bmailout2.hostsharing.net (Postfix) with ESMTPS id 7806A2800B489; Wed, 13 Sep 2023 06:25:22 +0200 (CEST) Received: by h08.hostsharing.net (Postfix, from userid 100393) id 562503FC2AD; Wed, 13 Sep 2023 06:25:22 +0200 (CEST) Date: Wed, 13 Sep 2023 06:25:22 +0200 From: Lukas Wunner To: Mario Limonciello Cc: Bjorn Helgaas , "Rafael J . Wysocki" , Mika Westerberg , Hans de Goede , Shyam Sundar S K , "open list:X86 PLATFORM DRIVERS" , "open list:PCI SUBSYSTEM" , linux-pm@vger.kernel.org, "open list:USB XHCI DRIVER" , iain@orangesquash.org.uk Subject: Re: [PATCH v18 2/2] PCI: Add a quirk for AMD PCIe root ports w/ USB4 controllers Message-ID: <20230913042522.GB1359@wunner.de> References: <20230913040832.114610-1-mario.limonciello@amd.com> <20230913040832.114610-3-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230913040832.114610-3-mario.limonciello@amd.com> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org On Tue, Sep 12, 2023 at 11:08:32PM -0500, Mario Limonciello wrote: > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -2752,6 +2752,11 @@ int pci_prepare_to_sleep(struct pci_dev *dev) > if (target_state == PCI_POWER_ERROR) > return -EIO; > > + /* quirk to avoid setting D3 */ > + if (wakeup && dev->dev_flags & PCI_DEV_FLAGS_NO_WAKE_D3 && > + (target_state == PCI_D3hot || target_state == PCI_D3cold)) > + target_state = PCI_D0; > + > pci_enable_wake(dev, target_state, wakeup); > > error = pci_set_power_state(dev, target_state); Would it be possible to just add the affected system to bridge_d3_blacklist[]? Or would that defeat power management of other (non-affected) Root Ports in the same machine? There's already PCI_DEV_FLAGS_NO_D3, would it be possible to just reuse that instead of adding another codepath for D3 quirks? Thanks, Lukas