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From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Sanath S <Sanath.S@amd.com>
Cc: mario.limonciello@amd.com, andreas.noever@gmail.com,
	michael.jamet@intel.com, YehezkelShB@gmail.com,
	linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [Patch v2 1/2] thunderbolt: Introduce tb_switch_reset_ports(), tb_port_reset() and usb4_port_reset()
Date: Wed, 13 Dec 2023 07:59:41 +0200	[thread overview]
Message-ID: <20231213055941.GJ1074920@black.fi.intel.com> (raw)
In-Reply-To: <20231212191635.2022520-2-Sanath.S@amd.com>

On Wed, Dec 13, 2023 at 12:46:34AM +0530, Sanath S wrote:
> Introduce the tb_switch_reset_ports() function that resets the
> downstream ports of a given switch. This helps us reset the USB4
> links created by boot firmware during the init sequence.
> 
> Introduce the tb_port_reset() helper function that resets the
> given port.
> 
> Introduce the usb4_port_reset() function that performs the DPR
> of a given port. This function follows the CM guide specification 7.3
> 
> Suggested-by: Mario Limonciello <mario.limonciello@amd.com>
> Signed-off-by: Sanath S <Sanath.S@amd.com>
> ---
>  drivers/thunderbolt/switch.c  | 35 +++++++++++++++++++++++++++++++
>  drivers/thunderbolt/tb.h      |  2 ++
>  drivers/thunderbolt/tb_regs.h |  1 +
>  drivers/thunderbolt/usb4.c    | 39 +++++++++++++++++++++++++++++++++++
>  4 files changed, 77 insertions(+)
> 
> diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
> index 44e9b09de47a..ef7ed92fd48e 100644
> --- a/drivers/thunderbolt/switch.c
> +++ b/drivers/thunderbolt/switch.c
> @@ -626,6 +626,19 @@ int tb_port_unlock(struct tb_port *port)
>  	return 0;
>  }
>  
> +/**
> + * tb_port_reset() - Reset downstream port
> + * @port: Port to reset
> + *
> + * Helps to reconfigure the USB4 link by resetting the downstream port.
> + *
> + * Return: Returns 0 on success or an error code on failure.
> + */
> +static int tb_port_reset(struct tb_port *port)
> +{
> +	return usb4_port_reset(port);
> +}
> +
>  static int __tb_port_enable(struct tb_port *port, bool enable)
>  {
>  	int ret;
> @@ -1547,6 +1560,28 @@ static void tb_dump_switch(const struct tb *tb, const struct tb_switch *sw)
>  	       regs->__unknown1, regs->__unknown4);
>  }
>  
> +/**
> + * tb_switch_reset_ports() - Reset downstream ports of switch.

Drop the '.'

> + * @sw: Switch whose ports need to be reset.
> + *
> + * This is applicable only for USB4 routers.
> + * tb_switch_is_usb4() needs to be called before calling this
> + * function.

This should fit into 2 lines:

	* This is applicable only for USB4 routers. tb_switch_is_usb4()
	* needs to be called before calling this function.

> + *
> + * Return: Returns 0 on success or an error code on failure.

Specifically returns %-EOPNOTSUPP if the router does not support this
(e.g is not USB4 router).

> + */
> +int tb_switch_reset_ports(struct tb_switch *sw)
> +{
> +	struct tb_port *port;
> +	int ret = -EOPNOTSUPP;

Reverse christmas tree:

	int ret = -EOPNOTSUPP;
	struct tb_port *port;

> +
> +	tb_switch_for_each_port(sw, port) {
> +		if (tb_port_is_null(port) && port->cap_usb4)
> +			return tb_port_reset(port);

Now you run this only once for the first lane adapter it finds.

How much you actually tested this patch series? :(

Since we are already in -rc5 it is unlikely that behavioral changes like
this will go to the next release (v6.8-rc1), so you have all that time
to make sure your patches work as expected.

> +	}
> +	return ret;
> +}
> +
>  /**
>   * tb_switch_reset() - reconfigure route, enable and send TB_CFG_PKG_RESET
>   * @sw: Switch to reset
> diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
> index e299e53473ae..f2687ec4ac53 100644
> --- a/drivers/thunderbolt/tb.h
> +++ b/drivers/thunderbolt/tb.h
> @@ -797,6 +797,7 @@ void tb_switch_remove(struct tb_switch *sw);
>  void tb_switch_suspend(struct tb_switch *sw, bool runtime);
>  int tb_switch_resume(struct tb_switch *sw);
>  int tb_switch_reset(struct tb_switch *sw);
> +int tb_switch_reset_ports(struct tb_switch *sw);
>  int tb_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit,
>  			   u32 value, int timeout_msec);
>  void tb_sw_set_unplugged(struct tb_switch *sw);
> @@ -1281,6 +1282,7 @@ struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
>  int usb4_switch_add_ports(struct tb_switch *sw);
>  void usb4_switch_remove_ports(struct tb_switch *sw);
>  
> +int usb4_port_reset(struct tb_port *port);
>  int usb4_port_unlock(struct tb_port *port);
>  int usb4_port_hotplug_enable(struct tb_port *port);
>  int usb4_port_configure(struct tb_port *port);
> diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h
> index 87e4795275fe..d49530bc0d53 100644
> --- a/drivers/thunderbolt/tb_regs.h
> +++ b/drivers/thunderbolt/tb_regs.h
> @@ -389,6 +389,7 @@ struct tb_regs_port_header {
>  #define PORT_CS_18_CSA				BIT(22)
>  #define PORT_CS_18_TIP				BIT(24)
>  #define PORT_CS_19				0x13
> +#define PORT_CS_19_DPR				BIT(0)
>  #define PORT_CS_19_PC				BIT(3)
>  #define PORT_CS_19_PID				BIT(4)
>  #define PORT_CS_19_WOC				BIT(16)
> diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c
> index 4277733d0021..c8a4bf33ed1c 100644
> --- a/drivers/thunderbolt/usb4.c
> +++ b/drivers/thunderbolt/usb4.c
> @@ -1073,6 +1073,45 @@ void usb4_switch_remove_ports(struct tb_switch *sw)
>  	}
>  }
>  
> +/**
> + * usb4_port_reset() - Reset USB4 downsteam port
> + * @port: USB4 port to reset.
> + *
> + * Helps to reconfigure USB4 link by resetting downstream port.
> + *
> + * Return: Returns 0 on success or an error code on failure.
> + */
> +int usb4_port_reset(struct tb_port *port)
> +{
> +	u32 val = 0;

This initialization is actually not needed.

> +	int ret;
> +
> +	ret = tb_port_read(port, &val, TB_CFG_PORT,
> +			port->cap_usb4 + PORT_CS_19, 1);
> +	if (ret)
> +		return ret;
> +
> +	val = val | PORT_CS_19_DPR;

val |= PORT_CS_19_DPR;

Same as you do below with &= ~..

> +	ret = tb_port_write(port, &val, TB_CFG_PORT,
> +			port->cap_usb4 + PORT_CS_19, 1);
> +	if (ret)
> +		return ret;
> +
> +	/* Wait for 10ms after requesting downstream port reset */
> +	usleep_range(10000, 15000);
> +
> +	ret = tb_port_read(port, &val, TB_CFG_PORT,
> +			port->cap_usb4 + PORT_CS_19, 1);
> +	if (ret)
> +		return ret;

Do you really need to read it back from the hardware here?

> +
> +	val &= ~PORT_CS_19_DPR;
> +	ret = tb_port_write(port, &val, TB_CFG_PORT,
> +			port->cap_usb4 + PORT_CS_19, 1);
> +
> +	return ret;

This can be simply

	return tb_port_write(port, &val, TB_CFG_PORT,
			     port->cap_usb4 + PORT_CS_19, 1);

> +}
> +
>  /**
>   * usb4_port_unlock() - Unlock USB4 downstream port
>   * @port: USB4 port to unlock
> -- 
> 2.34.1

  parent reply	other threads:[~2023-12-13  5:59 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-12 19:16 [PATCH v2 0/2] Add support for downstream port reset(DPR) Sanath S
2023-12-12 19:16 ` [Patch v2 1/2] thunderbolt: Introduce tb_switch_reset_ports(), tb_port_reset() and usb4_port_reset() Sanath S
2023-12-12 19:26   ` Mario Limonciello
2023-12-13  5:59   ` Mika Westerberg [this message]
2023-12-13 11:58     ` Sanath S
2023-12-13 12:04       ` Mika Westerberg
2023-12-12 19:16 ` [Patch v2 2/2] thunderbolt: Teardown tunnels and reset downstream ports created by boot firmware Sanath S
2023-12-12 19:24   ` Mario Limonciello
2023-12-12 19:25     ` Mario Limonciello
2023-12-13  5:49   ` Mika Westerberg
2023-12-13  6:18     ` Mika Westerberg
2023-12-13  6:23       ` Mika Westerberg
2023-12-13 10:34         ` Sanath S
2023-12-13 11:52           ` Mika Westerberg
2023-12-14  6:38             ` Sanath S
2023-12-14  7:07               ` Mika Westerberg
2023-12-14  7:20                 ` Sanath S
2023-12-14  7:32                   ` Mika Westerberg
2023-12-14 15:30                     ` Sanath S
2023-12-15 11:55                       ` Mika Westerberg
2023-12-15 13:54                         ` Sanath S
2023-12-15 14:02                           ` Mika Westerberg
2023-12-18 10:20                             ` Sanath S
2023-12-18 10:42                               ` Mika Westerberg
2023-12-18 11:19                                 ` Sanath S
2023-12-18 11:31                                   ` Mika Westerberg
2023-12-18 12:23                                     ` Mika Westerberg
2023-12-18 13:05                                       ` Sanath S
2023-12-18 13:18                                         ` Mika Westerberg
2023-12-19  9:11                                           ` Sanath S
2023-12-19 12:26                                             ` Mika Westerberg
2023-12-19 14:35                                               ` Sanath S
2023-12-19 18:04                                                 ` Mika Westerberg
2023-12-20 12:58                                                   ` Mika Westerberg
2023-12-20 17:01                                                     ` Sanath S
2023-12-21  9:31                                                       ` Sanath S
2023-12-21  9:53                                                         ` Mika Westerberg
2024-01-03 14:15                                                           ` Sanath S
2024-01-03 17:17                                                             ` Mika Westerberg
2024-01-04 13:47                                                               ` Sanath S
2024-01-04 13:50                                                               ` Sanath S
2024-01-05  7:08                                                                 ` Mika Westerberg
2024-01-08  4:56                                                                   ` Sanath S
2024-01-10 14:32                                                                     ` Mika Westerberg
2024-01-04 16:49                                               ` Sanath S
2024-01-05  7:06                                                 ` Mika Westerberg

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