From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Sanath S <sanaths2@amd.com>
Cc: Sanath S <Sanath.S@amd.com>,
mario.limonciello@amd.com, andreas.noever@gmail.com,
michael.jamet@intel.com, YehezkelShB@gmail.com,
linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [Patch v2 2/2] thunderbolt: Teardown tunnels and reset downstream ports created by boot firmware
Date: Fri, 5 Jan 2024 09:06:11 +0200 [thread overview]
Message-ID: <20240105070611.GM2543524@black.fi.intel.com> (raw)
In-Reply-To: <558fb39a-470d-16e3-0043-510e6b4b3f8e@amd.com>
On Thu, Jan 04, 2024 at 10:19:20PM +0530, Sanath S wrote:
>
> On 12/19/2023 5:56 PM, Mika Westerberg wrote:
> > On Tue, Dec 19, 2023 at 02:41:08PM +0530, Sanath S wrote:
> > > On 12/18/2023 6:48 PM, Mika Westerberg wrote:
> > > > On Mon, Dec 18, 2023 at 06:35:13PM +0530, Sanath S wrote:
> > > > > On 12/18/2023 5:53 PM, Mika Westerberg wrote:
> > > > > > On Mon, Dec 18, 2023 at 01:31:51PM +0200, Mika Westerberg wrote:
> > > > > > > On Mon, Dec 18, 2023 at 04:49:13PM +0530, Sanath S wrote:
> > > > > > > > > The discover part should not do anything (like write the hardware) so
> > > > > > > > > perhaps it is just some timing thing (but that's weird too).
> > > > > > > > >
> > > > > > > > > I think we should do something like this:
> > > > > > > > >
> > > > > > > > > 1. Disable all enabled protocol adapters (reset them to defaults).
> > > > > > > > > 2. Clear all protocol adapter paths.
> > > > > > > > > 3. Issue DPR over all enabled USB4 ports.
> > > > > > > > >
> > > > > > > > > BTW, what you mean "didn't work"?
> > > > > > > > Path activation would go fine after DPR like below:
> > > > > > > >
> > > > > > > > [ 15.090905] thunderbolt 0000:c4:00.5: 0:5 <-> 2:9 (PCI): activating
> > > > > > > > [ 15.090932] thunderbolt 0000:c4:00.5: activating PCIe Down path from 0:5
> > > > > > > > to 2:9
> > > > > > > > [ 15.091602] thunderbolt 0000:c4:00.5: activating PCIe Up path from 2:9 to
> > > > > > > > 0:5
> > > > > > > >
> > > > > > > > But, PCIE enumeration doesn't happen (pcie link up will not happen, will not
> > > > > > > > see below logs)
> > > > > > > > [ 15.134223] pcieport 0000:00:03.1: pciehp: Slot(0-1): Card present
> > > > > > > > [ 15.134243] pcieport 0000:00:03.1: pciehp: Slot(0-1): Link Up
> > > > > > > Okay, what if you like reset the PCIe adapter config spaces back to the
> > > > > > > defaults? Just as an experiment.
> > > > > > If this turns out to be really complex then I guess it is better to do
> > > > > > it like you did originally using discovery but at least it would be nice
> > > > > > to see what the end result of this experiment looks like :)
> > > I feel it's better to go with discover and then reset for now (as v3).
> > > I'll keep this experiment as "to do" and will send out when I crack it down.
> I got what we were missing. It's not required to do a discover_tunnel before
> we tear down.
>
> We were resetting the downstream port and do a "continue;"
> So, we were not cleaning up its path. Actually we have to cleanup its path
> after DPR.
>
> After changing it, It works without any tunnel_discover() api's.
Makes sense, good finding.
prev parent reply other threads:[~2024-01-05 7:06 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 19:16 [PATCH v2 0/2] Add support for downstream port reset(DPR) Sanath S
2023-12-12 19:16 ` [Patch v2 1/2] thunderbolt: Introduce tb_switch_reset_ports(), tb_port_reset() and usb4_port_reset() Sanath S
2023-12-12 19:26 ` Mario Limonciello
2023-12-13 5:59 ` Mika Westerberg
2023-12-13 11:58 ` Sanath S
2023-12-13 12:04 ` Mika Westerberg
2023-12-12 19:16 ` [Patch v2 2/2] thunderbolt: Teardown tunnels and reset downstream ports created by boot firmware Sanath S
2023-12-12 19:24 ` Mario Limonciello
2023-12-12 19:25 ` Mario Limonciello
2023-12-13 5:49 ` Mika Westerberg
2023-12-13 6:18 ` Mika Westerberg
2023-12-13 6:23 ` Mika Westerberg
2023-12-13 10:34 ` Sanath S
2023-12-13 11:52 ` Mika Westerberg
2023-12-14 6:38 ` Sanath S
2023-12-14 7:07 ` Mika Westerberg
2023-12-14 7:20 ` Sanath S
2023-12-14 7:32 ` Mika Westerberg
2023-12-14 15:30 ` Sanath S
2023-12-15 11:55 ` Mika Westerberg
2023-12-15 13:54 ` Sanath S
2023-12-15 14:02 ` Mika Westerberg
2023-12-18 10:20 ` Sanath S
2023-12-18 10:42 ` Mika Westerberg
2023-12-18 11:19 ` Sanath S
2023-12-18 11:31 ` Mika Westerberg
2023-12-18 12:23 ` Mika Westerberg
2023-12-18 13:05 ` Sanath S
2023-12-18 13:18 ` Mika Westerberg
2023-12-19 9:11 ` Sanath S
2023-12-19 12:26 ` Mika Westerberg
2023-12-19 14:35 ` Sanath S
2023-12-19 18:04 ` Mika Westerberg
2023-12-20 12:58 ` Mika Westerberg
2023-12-20 17:01 ` Sanath S
2023-12-21 9:31 ` Sanath S
2023-12-21 9:53 ` Mika Westerberg
2024-01-03 14:15 ` Sanath S
2024-01-03 17:17 ` Mika Westerberg
2024-01-04 13:47 ` Sanath S
2024-01-04 13:50 ` Sanath S
2024-01-05 7:08 ` Mika Westerberg
2024-01-08 4:56 ` Sanath S
2024-01-10 14:32 ` Mika Westerberg
2024-01-04 16:49 ` Sanath S
2024-01-05 7:06 ` Mika Westerberg [this message]
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