From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Yehezkel Bernat <YehezkelShB@gmail.com>,
Michael Jamet <michael.jamet@intel.com>,
Lukas Wunner <lukas@wunner.de>,
Andreas Noever <andreas.noever@gmail.com>
Cc: linux-usb@vger.kernel.org, Greg KH <gregkh@linuxfoundation.org>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: [PATCH v2 5/6] thunderbolt: Make margining functions accept target and retimer index
Date: Fri, 14 Jun 2024 15:15:11 +0300 [thread overview]
Message-ID: <20240614121512.1361184-6-mika.westerberg@linux.intel.com> (raw)
In-Reply-To: <20240614121512.1361184-1-mika.westerberg@linux.intel.com>
In order to add lane margining support for retimers make the margining
functions take sideband target and retimer index as parameters. This
makes it possible to access both router and retimer sideband using the
same functions.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
drivers/thunderbolt/debugfs.c | 16 ++++++-----
drivers/thunderbolt/tb.h | 15 ++++++-----
drivers/thunderbolt/usb4.c | 51 +++++++++++++++++++++--------------
3 files changed, 50 insertions(+), 32 deletions(-)
diff --git a/drivers/thunderbolt/debugfs.c b/drivers/thunderbolt/debugfs.c
index 0e871c7ae9c0..87b2c91a4656 100644
--- a/drivers/thunderbolt/debugfs.c
+++ b/drivers/thunderbolt/debugfs.c
@@ -774,22 +774,25 @@ static int margining_run_write(void *data, u64 val)
if (margining->software) {
tb_port_dbg(port, "running software %s lane margining for lanes %u\n",
margining->time ? "time" : "voltage", margining->lanes);
- ret = usb4_port_sw_margin(port, margining->lanes, margining->time,
+ ret = usb4_port_sw_margin(port, USB4_SB_TARGET_ROUTER, 0,
+ margining->lanes, margining->time,
margining->right_high,
USB4_MARGIN_SW_COUNTER_CLEAR);
if (ret)
goto out_clx;
- ret = usb4_port_sw_margin_errors(port, &margining->results[0]);
+ ret = usb4_port_sw_margin_errors(port, USB4_SB_TARGET_ROUTER, 0,
+ &margining->results[0]);
} else {
tb_port_dbg(port, "running hardware %s lane margining for lanes %u\n",
margining->time ? "time" : "voltage", margining->lanes);
/* Clear the results */
margining->results[0] = 0;
margining->results[1] = 0;
- ret = usb4_port_hw_margin(port, margining->lanes,
- margining->ber_level, margining->time,
- margining->right_high, margining->results);
+ ret = usb4_port_hw_margin(port, USB4_SB_TARGET_ROUTER, 0,
+ margining->lanes, margining->ber_level,
+ margining->time, margining->right_high,
+ margining->results);
}
out_clx:
@@ -1063,7 +1066,8 @@ static void margining_port_init(struct tb_port *port)
margining->port = port;
- ret = usb4_port_margining_caps(port, margining->caps);
+ ret = usb4_port_margining_caps(port, USB4_SB_TARGET_ROUTER, 0,
+ margining->caps);
if (ret) {
kfree(margining);
return;
diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
index 1a53d18223d9..2f3de3d3c2e0 100644
--- a/drivers/thunderbolt/tb.h
+++ b/drivers/thunderbolt/tb.h
@@ -1349,13 +1349,16 @@ int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target, u8 index
int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
u8 index, u8 reg, const void *buf, u8 size);
-int usb4_port_margining_caps(struct tb_port *port, u32 *caps);
-int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
- unsigned int ber_level, bool timing, bool right_high,
- u32 *results);
-int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing,
+int usb4_port_margining_caps(struct tb_port *port, enum usb4_sb_target target,
+ u8 index, u32 *caps);
+int usb4_port_hw_margin(struct tb_port *port, enum usb4_sb_target target,
+ u8 index, unsigned int lanes, unsigned int ber_level,
+ bool timing, bool right_high, u32 *results);
+int usb4_port_sw_margin(struct tb_port *port, enum usb4_sb_target target,
+ u8 index, unsigned int lanes, bool timing,
bool right_high, u32 counter);
-int usb4_port_sw_margin_errors(struct tb_port *port, u32 *errors);
+int usb4_port_sw_margin_errors(struct tb_port *port, enum usb4_sb_target target,
+ u8 index, u32 *errors);
int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index);
int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index);
diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c
index 140e0da3a8de..d952de07493f 100644
--- a/drivers/thunderbolt/usb4.c
+++ b/drivers/thunderbolt/usb4.c
@@ -1628,26 +1628,31 @@ int usb4_port_asym_start(struct tb_port *port)
/**
* usb4_port_margining_caps() - Read USB4 port marginig capabilities
* @port: USB4 port
+ * @target: Sideband target
+ * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
* @caps: Array with at least two elements to hold the results
*
* Reads the USB4 port lane margining capabilities into @caps.
*/
-int usb4_port_margining_caps(struct tb_port *port, u32 *caps)
+int usb4_port_margining_caps(struct tb_port *port, enum usb4_sb_target target,
+ u8 index, u32 *caps)
{
int ret;
- ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
+ ret = usb4_port_sb_op(port, target, index,
USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, 500);
if (ret)
return ret;
- return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
- USB4_SB_DATA, caps, sizeof(*caps) * 2);
+ return usb4_port_sb_read(port, target, index, USB4_SB_DATA, caps,
+ sizeof(*caps) * 2);
}
/**
* usb4_port_hw_margin() - Run hardware lane margining on port
* @port: USB4 port
+ * @target: Sideband target
+ * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
* @lanes: Which lanes to run (must match the port capabilities). Can be
* %0, %1 or %7.
* @ber_level: BER level contour value
@@ -1658,9 +1663,9 @@ int usb4_port_margining_caps(struct tb_port *port, u32 *caps)
* Runs hardware lane margining on USB4 port and returns the result in
* @results.
*/
-int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
- unsigned int ber_level, bool timing, bool right_high,
- u32 *results)
+int usb4_port_hw_margin(struct tb_port *port, enum usb4_sb_target target,
+ u8 index, unsigned int lanes, unsigned int ber_level,
+ bool timing, bool right_high, u32 *results)
{
u32 val;
int ret;
@@ -1674,23 +1679,25 @@ int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
val |= (ber_level << USB4_MARGIN_HW_BER_SHIFT) &
USB4_MARGIN_HW_BER_MASK;
- ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
- USB4_SB_METADATA, &val, sizeof(val));
+ ret = usb4_port_sb_write(port, target, index, USB4_SB_METADATA, &val,
+ sizeof(val));
if (ret)
return ret;
- ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
+ ret = usb4_port_sb_op(port, target, index,
USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, 2500);
if (ret)
return ret;
- return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
- USB4_SB_DATA, results, sizeof(*results) * 2);
+ return usb4_port_sb_read(port, target, index, USB4_SB_DATA, results,
+ sizeof(*results) * 2);
}
/**
* usb4_port_sw_margin() - Run software lane margining on port
* @port: USB4 port
+ * @target: Sideband target
+ * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
* @lanes: Which lanes to run (must match the port capabilities). Can be
* %0, %1 or %7.
* @timing: Perform timing margining instead of voltage
@@ -1701,7 +1708,8 @@ int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
* counters by calling usb4_port_sw_margin_errors(). Returns %0 in
* success and negative errno otherwise.
*/
-int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing,
+int usb4_port_sw_margin(struct tb_port *port, enum usb4_sb_target target,
+ u8 index, unsigned int lanes, bool timing,
bool right_high, u32 counter)
{
u32 val;
@@ -1715,34 +1723,37 @@ int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing,
val |= (counter << USB4_MARGIN_SW_COUNTER_SHIFT) &
USB4_MARGIN_SW_COUNTER_MASK;
- ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
- USB4_SB_METADATA, &val, sizeof(val));
+ ret = usb4_port_sb_write(port, target, index, USB4_SB_METADATA, &val,
+ sizeof(val));
if (ret)
return ret;
- return usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
+ return usb4_port_sb_op(port, target, index,
USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, 2500);
}
/**
* usb4_port_sw_margin_errors() - Read the software margining error counters
* @port: USB4 port
+ * @target: Sideband target
+ * @index: Retimer index if taget is %USB4_SB_TARGET_RETIMER
* @errors: Error metadata is copied here.
*
* This reads back the software margining error counters from the port.
* Returns %0 in success and negative errno otherwise.
*/
-int usb4_port_sw_margin_errors(struct tb_port *port, u32 *errors)
+int usb4_port_sw_margin_errors(struct tb_port *port, enum usb4_sb_target target,
+ u8 index, u32 *errors)
{
int ret;
- ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
+ ret = usb4_port_sb_op(port, target, index,
USB4_SB_OPCODE_READ_SW_MARGIN_ERR, 150);
if (ret)
return ret;
- return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
- USB4_SB_METADATA, errors, sizeof(*errors));
+ return usb4_port_sb_read(port, target, index, USB4_SB_METADATA, errors,
+ sizeof(*errors));
}
static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
--
2.43.0
next prev parent reply other threads:[~2024-06-14 12:15 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-14 12:15 [PATCH v2 0/6] thunderbolt: Sideband access and retimer lane margining support Mika Westerberg
2024-06-14 12:15 ` [PATCH v2 1/6] thunderbolt: Move usb4_port_margining_caps() declaration into correct place Mika Westerberg
2024-06-14 12:15 ` [PATCH v2 2/6] thunderbolt: Make usb4_port_sb_read/write() available outside of usb4.c Mika Westerberg
2024-06-14 12:15 ` [PATCH v2 3/6] thunderbolt: Add sideband register access to debugfs Mika Westerberg
2024-06-14 12:15 ` [PATCH v2 4/6] thunderbolt: Split out margining from USB4 port Mika Westerberg
2024-06-14 12:15 ` Mika Westerberg [this message]
2024-06-14 12:15 ` [PATCH v2 6/6] thunderbolt: Add receiver lane margining support for retimers Mika Westerberg
2024-06-14 12:19 ` [PATCH v2 0/6] thunderbolt: Sideband access and retimer lane margining support Greg KH
2024-06-14 12:37 ` Mika Westerberg
2024-06-14 12:55 ` Greg KH
2024-06-17 9:58 ` Mika Westerberg
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