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charset=utf-8 Content-Disposition: inline In-Reply-To: <844e3930-7b3d-46a1-ad90-bcecbb99c069@amd.com> On Fri, Jun 21, 2024 at 11:30:05AM -0500, Mario Limonciello wrote: > On 6/21/2024 01:19, Mika Westerberg wrote: > > Hi Mario, > > > > On Thu, Jun 20, 2024 at 01:36:56PM -0500, Mario Limonciello wrote: > > > On 6/20/2024 01:41, Mika Westerberg wrote: > > > > +CC Mario from AMD side to check that we are good and don't break > > > > anything accidentally. > > > > > > > > On Wed, Jun 19, 2024 at 04:03:01PM +0300, Mathias Nyman wrote: > > > > > The relationship between a USB4 Host Interface providing USB3 tunnels, > > > > > and tunneled USB3 devices is not represented in device hierarchy. > > > > > > > > > > This caused issues with power managment as devices may suspend and > > > > > resume in incorrect order. > > > > > A device link between the USB4 Host Interface and the USB3 xHCI was > > > > > originally added to solve this, preventing the USB4 Host Interface from > > > > > suspending if the USB3 xHCI Host was still active. > > > > > This unfortunately also prevents USB4 Host Interface from suspending even > > > > > if the USB3 xHCI Host is only serving native non-tunneled USB devices. > > > > > > > > > > Improve the current powermanagement situation by creating device links > > > > > directly from tunneled USB3 devices to the USB4 Host Interface they depend > > > > > on instead of a device link between the hosts. > > > > > This way USB4 host may suspend when the last tunneled device is > > > > > disconnected. > > > > > > > > > > Intel xHCI hosts are capable of reporting if connected USB3 devices are > > > > > tunneled via vendor specific capabilities. > > > > > Use this until a standard way is available. > > > > > > > > > > Mathias Nyman (4): > > > > > xhci: Add USB4 tunnel detection for USB3 devices on Intel hosts > > > > > usb: Add tunneled parameter to usb device structure > > > > > usb: acpi: add device link between tunneled USB3 device and USB4 Host > > > > > Interface > > > > > thunderbolt: Don't create device link from USB4 Host Interface to USB3 > > > > > xHC host > > > > > > > > > > drivers/thunderbolt/acpi.c | 40 ++++++------------------ > > > > > drivers/usb/core/usb-acpi.c | 52 ++++++++++++++++++++++++++++++++ > > > > > drivers/usb/host/xhci-ext-caps.h | 5 +++ > > > > > drivers/usb/host/xhci-hub.c | 29 ++++++++++++++++++ > > > > > drivers/usb/host/xhci.c | 12 ++++++++ > > > > > drivers/usb/host/xhci.h | 1 + > > > > > include/linux/usb.h | 2 ++ > > > > > 7 files changed, 111 insertions(+), 30 deletions(-) > > > > > > > > > > -- > > > > > 2.25.1 > > > > > > Hi Mika, > > > > > > Thanks for looping me in. Unfortunately with this is appears the XHCI > > > controller link never gets created. I've not checked functional impact from > > > this, but I'd guess there "should" be some functional problems too. > > > > Thanks for checking! > > > > I think the code that sets up the device link based on ->tunneled should > > do that always if the hardware cannot tell if this is native or tunneled > > link to keep the existing functionality and only do the "optimization" > > if the hardware is capable of identifying that. > > > > Perhaps it can be a callback provided by the xHCI controller driver > > (->is_tunneled()) that then defaults to true if the > > "usb4-host-interface" property is there and in case of Intel hardware > > also checks the proprietary register? > > So I think the problem is you will have an ordering dependency between the > two drivers for when the link gets created. > > Like if thunderbolt.ko loads you would end up with links to PCIe root port > for tunneling as well as XHCI controller. With this patch we only create links to PCIe Root/Downstream ports from Thunderbolt side and the USB core will deal with the USB ones. > Then xhci loads and you end up also adding links to individual ports. > Would you remove the link to the controller? See above. > And if the order is the other way around you end up with a larger state > machine. > > How about PCIe core provides a helper to know whether or not a PCIe device > will support the proprietary register? I think the xHCI can be non-PCIe device too (Apple silicon for instance). The links here are created dynamically and only if there is need (and support from the hardware) so we can let the USB4 controller enter D3hot if there is no USB 3.x tunnel needed.