* [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set
@ 2024-09-12 3:35 Xu Yang
2024-09-12 3:35 ` [PATCH 2/3] usb: chipidea: udc: improve dTD link logic Xu Yang
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Xu Yang @ 2024-09-12 3:35 UTC (permalink / raw)
To: peter.chen, gregkh; +Cc: linux-usb, imx, jun.li
As per USBSTS register description about UEI:
When completion of a USB transaction results in an error condition, this
bit is set by the Host/Device Controller. This bit is set along with the
USBINT bit, if the TD on which the error interrupt occurred also had its
interrupt on complete (IOC) bit set.
Currently, device controller will do nothing when endpoints met transfer
error if IOC didn't set on that error dTD since UI didn't assert too. This
will also handle UEI event as same as USBSTS.UI for such cases.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
drivers/usb/chipidea/udc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 69ef3cd8d4f8..b9ccf62e0a50 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -2063,7 +2063,7 @@ static irqreturn_t udc_irq(struct ci_hdrc *ci)
}
}
- if (USBi_UI & intr)
+ if ((USBi_UI | USBi_UEI) & intr)
isr_tr_complete_handler(ci);
if ((USBi_SLI & intr) && !(ci->suspended)) {
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/3] usb: chipidea: udc: improve dTD link logic
2024-09-12 3:35 [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set Xu Yang
@ 2024-09-12 3:35 ` Xu Yang
2024-09-12 4:54 ` Frank Li
2024-09-13 8:51 ` kernel test robot
2024-09-12 3:35 ` [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant Xu Yang
` (2 subsequent siblings)
3 siblings, 2 replies; 13+ messages in thread
From: Xu Yang @ 2024-09-12 3:35 UTC (permalink / raw)
To: peter.chen, gregkh; +Cc: linux-usb, imx, jun.li
Currently, ATDTW semaphore is used to safety link new dTD to dQH. But this
code has a bug when the endpoint is already in error before polling ATDTW
or just met error during polling ATDTW. In that cases, ATDTW will never
turn to 1 and the cpu will busy loop there.
When the endpoint met error, ENDPTSTAT will be cleared by HW. Therefore,
ENDPTSTAT should also be considered during this process. In case of
endpoint error, the current dTD should not be pushed to the head of dQH
since some dTDs may be still not executed. Therefore, the link logic is
also improved accordingly.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
drivers/usb/chipidea/udc.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index b9ccf62e0a50..0ab57b87b07b 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -612,10 +612,17 @@ static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
do {
hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n));
- } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW));
+ } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW) && tmp_stat);
hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0);
if (tmp_stat)
goto done;
+
+ /* In case of error, ENDPTSTAT will also turn into 0, then
+ * don't push this dTD to dQH head if current dTD pointer
+ * is not the last dTD in previous request.
+ */
+ if (hwep->qh.ptr->curr != prevlastnode->dma)
+ goto done;
}
/* QH configuration */
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant
2024-09-12 3:35 [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set Xu Yang
2024-09-12 3:35 ` [PATCH 2/3] usb: chipidea: udc: improve dTD link logic Xu Yang
@ 2024-09-12 3:35 ` Xu Yang
2024-09-12 5:13 ` Frank Li
2024-09-13 1:49 ` Peter Chen
2024-09-12 5:26 ` [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set Frank Li
2024-09-13 1:37 ` Peter Chen
3 siblings, 2 replies; 13+ messages in thread
From: Xu Yang @ 2024-09-12 3:35 UTC (permalink / raw)
To: peter.chen, gregkh; +Cc: linux-usb, imx, jun.li
When a endpoint met errors, the usb controller will firstly assert
related error bit in status filed of dTD, then ENDPTCOMPLETE will be
asserted. Finally, USBSTS.UEI will be set.
Due to isoc transfers are error-tolerant transfers, we can make isoc
endpoint a bit error tolerant on device mode too. In case of error,
it's possilbe to resume the endpoint by reprime the corresponding
endpoint.
When error occurs, this will allow error dTD be deleted from dQH and
giveback request to user. Then, a reprime/prime operation is executed
depends on whether dQH is empty or not. If dQH is not empty, reprime
will be done during dequeue process. If dQH is empty, prime will be
done when new dTD is linked. In this way, isoc transfer can be recovered
from a small number of errors.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
drivers/usb/chipidea/udc.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 0ab57b87b07b..b1a1be6439b6 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -683,6 +683,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
unsigned remaining_length;
unsigned actual = hwreq->req.length;
struct ci_hdrc *ci = hwep->ci;
+ bool is_isoc = hwep->type == USB_ENDPOINT_XFER_ISOC;
if (hwreq->req.status != -EALREADY)
return -EINVAL;
@@ -696,7 +697,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
int n = hw_ep_bit(hwep->num, hwep->dir);
if (ci->rev == CI_REVISION_24 ||
- ci->rev == CI_REVISION_22)
+ ci->rev == CI_REVISION_22 || is_isoc)
if (!hw_read(ci, OP_ENDPTSTAT, BIT(n)))
reprime_dtd(ci, hwep, node);
hwreq->req.status = -EALREADY;
@@ -707,7 +708,6 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
remaining_length >>= __ffs(TD_TOTAL_BYTES);
actual -= remaining_length;
- hwreq->req.status = tmptoken & TD_STATUS;
if ((TD_STATUS_HALTED & hwreq->req.status)) {
hwreq->req.status = -EPIPE;
break;
@@ -715,11 +715,13 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
hwreq->req.status = -EPROTO;
break;
} else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
- hwreq->req.status = -EILSEQ;
- break;
+ if (!is_isoc) {
+ hwreq->req.status = -EILSEQ;
+ break;
+ }
}
- if (remaining_length) {
+ if (remaining_length && !is_isoc) {
if (hwep->dir == TX) {
hwreq->req.status = -EPROTO;
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/3] usb: chipidea: udc: improve dTD link logic
2024-09-12 3:35 ` [PATCH 2/3] usb: chipidea: udc: improve dTD link logic Xu Yang
@ 2024-09-12 4:54 ` Frank Li
2024-09-13 1:52 ` Xu Yang
2024-09-13 8:51 ` kernel test robot
1 sibling, 1 reply; 13+ messages in thread
From: Frank Li @ 2024-09-12 4:54 UTC (permalink / raw)
To: Xu Yang; +Cc: peter.chen, gregkh, linux-usb, imx, jun.li
On Thu, Sep 12, 2024 at 11:35:50AM +0800, Xu Yang wrote:
> Currently, ATDTW semaphore is used to safety link new dTD to dQH. But this
> code has a bug when the endpoint is already in error before polling ATDTW
> or just met error during polling ATDTW. In that cases, ATDTW will never
> turn to 1 and the cpu will busy loop there.
It should be bug fixes, add fixes tag and cc stable.
>
> When the endpoint met error, ENDPTSTAT will be cleared by HW. Therefore,
> ENDPTSTAT should also be considered during this process. In case of
> endpoint error, the current dTD should not be pushed to the head of dQH
> since some dTDs may be still not executed. Therefore, the link logic is
> also improved accordingly.
>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
> drivers/usb/chipidea/udc.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index b9ccf62e0a50..0ab57b87b07b 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -612,10 +612,17 @@ static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> do {
> hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
> tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n));
> - } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW));
> + } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW) && tmp_stat);
> hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0);
> if (tmp_stat)
> goto done;
> +
> + /* In case of error, ENDPTSTAT will also turn into 0, then
> + * don't push this dTD to dQH head if current dTD pointer
> + * is not the last dTD in previous request.
> + */
OP_ENDPTSTAT will be clear by HW when the endpoint met err. This dTD don't
push to dQH if current dTD point is not the last one in previous request.
> + if (hwep->qh.ptr->curr != prevlastnode->dma)
> + goto done;
> }
>
> /* QH configuration */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant
2024-09-12 3:35 ` [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant Xu Yang
@ 2024-09-12 5:13 ` Frank Li
2024-09-13 1:55 ` Xu Yang
2024-09-13 1:49 ` Peter Chen
1 sibling, 1 reply; 13+ messages in thread
From: Frank Li @ 2024-09-12 5:13 UTC (permalink / raw)
To: Xu Yang; +Cc: peter.chen, gregkh, linux-usb, imx, jun.li
On Thu, Sep 12, 2024 at 11:35:51AM +0800, Xu Yang wrote:
usb: chipidea: udc: improve error recovery for ISO transfer
> When a endpoint met errors, the usb controller will firstly assert
> related error bit in status filed of dTD, then ENDPTCOMPLETE will be
> asserted. Finally, USBSTS.UEI will be set.
Look like this information is not related with this patch.
>
> Due to isoc transfers are error-tolerant transfers, we can make isoc
> endpoint a bit error tolerant on device mode too. In case of error,
> it's possilbe to resume the endpoint by reprime the corresponding
> endpoint.
Impove device mode ISO transfer error tolerant by reprime the corresponding
endpont.
>
> When error occurs, this will allow error dTD be deleted from dQH and
> giveback request to user. Then, a reprime/prime operation is executed
> depends on whether dQH is empty or not. If dQH is not empty, reprime
> will be done during dequeue process. If dQH is empty, prime will be
> done when new dTD is linked. In this way, isoc transfer can be recovered
> from a small number of errors.
The recovery steps when error occurs:
- Delete the error dTD from dQH and giveback request to user.
- Do reprime if dQH is not empty.
- Do prime when new dTD is queued if dQH is empty
>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
> drivers/usb/chipidea/udc.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index 0ab57b87b07b..b1a1be6439b6 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -683,6 +683,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> unsigned remaining_length;
> unsigned actual = hwreq->req.length;
> struct ci_hdrc *ci = hwep->ci;
> + bool is_isoc = hwep->type == USB_ENDPOINT_XFER_ISOC;
>
> if (hwreq->req.status != -EALREADY)
> return -EINVAL;
> @@ -696,7 +697,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> int n = hw_ep_bit(hwep->num, hwep->dir);
>
> if (ci->rev == CI_REVISION_24 ||
> - ci->rev == CI_REVISION_22)
> + ci->rev == CI_REVISION_22 || is_isoc)
> if (!hw_read(ci, OP_ENDPTSTAT, BIT(n)))
> reprime_dtd(ci, hwep, node);
> hwreq->req.status = -EALREADY;
> @@ -707,7 +708,6 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> remaining_length >>= __ffs(TD_TOTAL_BYTES);
> actual -= remaining_length;
>
> - hwreq->req.status = tmptoken & TD_STATUS;
> if ((TD_STATUS_HALTED & hwreq->req.status)) {
> hwreq->req.status = -EPIPE;
> break;
> @@ -715,11 +715,13 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> hwreq->req.status = -EPROTO;
> break;
> } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
> - hwreq->req.status = -EILSEQ;
> - break;
> + if (!is_isoc) {
> + hwreq->req.status = -EILSEQ;
> + break;
> + }
> }
>
> - if (remaining_length) {
> + if (remaining_length && !is_isoc) {
> if (hwep->dir == TX) {
> hwreq->req.status = -EPROTO;
> break;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set
2024-09-12 3:35 [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set Xu Yang
2024-09-12 3:35 ` [PATCH 2/3] usb: chipidea: udc: improve dTD link logic Xu Yang
2024-09-12 3:35 ` [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant Xu Yang
@ 2024-09-12 5:26 ` Frank Li
2024-09-13 3:21 ` Xu Yang
2024-09-13 1:37 ` Peter Chen
3 siblings, 1 reply; 13+ messages in thread
From: Frank Li @ 2024-09-12 5:26 UTC (permalink / raw)
To: Xu Yang; +Cc: peter.chen, gregkh, linux-usb, imx, jun.li
On Thu, Sep 12, 2024 at 11:35:49AM +0800, Xu Yang wrote:
> As per USBSTS register description about UEI:
>
> When completion of a USB transaction results in an error condition, this
> bit is set by the Host/Device Controller. This bit is set along with the
> USBINT bit, if the TD on which the error interrupt occurred also had its
> interrupt on complete (IOC) bit set.
>
> Currently, device controller will do nothing when endpoints met transfer
> error if IOC didn't set on that error dTD since UI didn't assert too. This
> will also handle UEI event as same as USBSTS.UI for such cases.
UI is set only when IOC set. Add checking UEI to fix miss call
isr_tr_complete_handler() when IOC have not set and transfer error happen.
If it is user visiable issue, add fix tag and cc stable.
>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
> drivers/usb/chipidea/udc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index 69ef3cd8d4f8..b9ccf62e0a50 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -2063,7 +2063,7 @@ static irqreturn_t udc_irq(struct ci_hdrc *ci)
> }
> }
>
> - if (USBi_UI & intr)
> + if ((USBi_UI | USBi_UEI) & intr)
Does it work if check UEI only?
Frank
> isr_tr_complete_handler(ci);
>
> if ((USBi_SLI & intr) && !(ci->suspended)) {
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set
2024-09-12 3:35 [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set Xu Yang
` (2 preceding siblings ...)
2024-09-12 5:26 ` [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set Frank Li
@ 2024-09-13 1:37 ` Peter Chen
3 siblings, 0 replies; 13+ messages in thread
From: Peter Chen @ 2024-09-13 1:37 UTC (permalink / raw)
To: Xu Yang; +Cc: gregkh, linux-usb, imx, jun.li
On 24-09-12 11:35:49, Xu Yang wrote:
> As per USBSTS register description about UEI:
>
> When completion of a USB transaction results in an error condition, this
> bit is set by the Host/Device Controller. This bit is set along with the
> USBINT bit, if the TD on which the error interrupt occurred also had its
> interrupt on complete (IOC) bit set.
>
> Currently, device controller will do nothing when endpoints met transfer
> error if IOC didn't set on that error dTD since UI didn't assert too. This
> will also handle UEI event as same as USBSTS.UI for such cases.
>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Peter Chen <peter.chen@kernel.com>
> ---
> drivers/usb/chipidea/udc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index 69ef3cd8d4f8..b9ccf62e0a50 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -2063,7 +2063,7 @@ static irqreturn_t udc_irq(struct ci_hdrc *ci)
> }
> }
>
> - if (USBi_UI & intr)
> + if ((USBi_UI | USBi_UEI) & intr)
> isr_tr_complete_handler(ci);
>
> if ((USBi_SLI & intr) && !(ci->suspended)) {
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant
2024-09-12 3:35 ` [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant Xu Yang
2024-09-12 5:13 ` Frank Li
@ 2024-09-13 1:49 ` Peter Chen
2024-09-13 3:12 ` Xu Yang
1 sibling, 1 reply; 13+ messages in thread
From: Peter Chen @ 2024-09-13 1:49 UTC (permalink / raw)
To: Xu Yang; +Cc: gregkh, linux-usb, imx, jun.li
On 24-09-12 11:35:51, Xu Yang wrote:
> When a endpoint met errors, the usb controller will firstly assert
> related error bit in status filed of dTD, then ENDPTCOMPLETE will be
> asserted. Finally, USBSTS.UEI will be set.
>
> Due to isoc transfers are error-tolerant transfers, we can make isoc
> endpoint a bit error tolerant on device mode too. In case of error,
> it's possilbe to resume the endpoint by reprime the corresponding
> endpoint.
>
> When error occurs, this will allow error dTD be deleted from dQH and
> giveback request to user. Then, a reprime/prime operation is executed
> depends on whether dQH is empty or not. If dQH is not empty, reprime
> will be done during dequeue process. If dQH is empty, prime will be
> done when new dTD is linked. In this way, isoc transfer can be recovered
> from a small number of errors.
>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
> drivers/usb/chipidea/udc.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> index 0ab57b87b07b..b1a1be6439b6 100644
> --- a/drivers/usb/chipidea/udc.c
> +++ b/drivers/usb/chipidea/udc.c
> @@ -683,6 +683,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> unsigned remaining_length;
> unsigned actual = hwreq->req.length;
> struct ci_hdrc *ci = hwep->ci;
> + bool is_isoc = hwep->type == USB_ENDPOINT_XFER_ISOC;
>
> if (hwreq->req.status != -EALREADY)
> return -EINVAL;
> @@ -696,7 +697,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> int n = hw_ep_bit(hwep->num, hwep->dir);
>
> if (ci->rev == CI_REVISION_24 ||
> - ci->rev == CI_REVISION_22)
> + ci->rev == CI_REVISION_22 || is_isoc)
> if (!hw_read(ci, OP_ENDPTSTAT, BIT(n)))
> reprime_dtd(ci, hwep, node);
> hwreq->req.status = -EALREADY;
> @@ -707,7 +708,6 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> remaining_length >>= __ffs(TD_TOTAL_BYTES);
> actual -= remaining_length;
>
> - hwreq->req.status = tmptoken & TD_STATUS;
Non-ISO dTD may need error status? You may refine code by ISO and
non-ISOC.
Peter
> if ((TD_STATUS_HALTED & hwreq->req.status)) {
> hwreq->req.status = -EPIPE;
> break;
> @@ -715,11 +715,13 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> hwreq->req.status = -EPROTO;
> break;
> } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
> - hwreq->req.status = -EILSEQ;
> - break;
> + if (!is_isoc) {
> + hwreq->req.status = -EILSEQ;
> + break;
> + }
> }
>
> - if (remaining_length) {
> + if (remaining_length && !is_isoc) {
> if (hwep->dir == TX) {
> hwreq->req.status = -EPROTO;
> break;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/3] usb: chipidea: udc: improve dTD link logic
2024-09-12 4:54 ` Frank Li
@ 2024-09-13 1:52 ` Xu Yang
0 siblings, 0 replies; 13+ messages in thread
From: Xu Yang @ 2024-09-13 1:52 UTC (permalink / raw)
To: Frank Li; +Cc: peter.chen, gregkh, linux-usb, imx, jun.li
On Thu, Sep 12, 2024 at 12:54:53AM -0400, Frank Li wrote:
> On Thu, Sep 12, 2024 at 11:35:50AM +0800, Xu Yang wrote:
> > Currently, ATDTW semaphore is used to safety link new dTD to dQH. But this
> > code has a bug when the endpoint is already in error before polling ATDTW
> > or just met error during polling ATDTW. In that cases, ATDTW will never
> > turn to 1 and the cpu will busy loop there.
>
> It should be bug fixes, add fixes tag and cc stable.
Okay.
>
> >
> > When the endpoint met error, ENDPTSTAT will be cleared by HW. Therefore,
> > ENDPTSTAT should also be considered during this process. In case of
> > endpoint error, the current dTD should not be pushed to the head of dQH
> > since some dTDs may be still not executed. Therefore, the link logic is
> > also improved accordingly.
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> > ---
> > drivers/usb/chipidea/udc.c | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> > index b9ccf62e0a50..0ab57b87b07b 100644
> > --- a/drivers/usb/chipidea/udc.c
> > +++ b/drivers/usb/chipidea/udc.c
> > @@ -612,10 +612,17 @@ static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> > do {
> > hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
> > tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n));
> > - } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW));
> > + } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW) && tmp_stat);
> > hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0);
> > if (tmp_stat)
> > goto done;
> > +
> > + /* In case of error, ENDPTSTAT will also turn into 0, then
> > + * don't push this dTD to dQH head if current dTD pointer
> > + * is not the last dTD in previous request.
> > + */
>
> OP_ENDPTSTAT will be clear by HW when the endpoint met err. This dTD don't
> push to dQH if current dTD point is not the last one in previous request.
Okay, will replace with it.
Thanks,
Xu Yang
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant
2024-09-12 5:13 ` Frank Li
@ 2024-09-13 1:55 ` Xu Yang
0 siblings, 0 replies; 13+ messages in thread
From: Xu Yang @ 2024-09-13 1:55 UTC (permalink / raw)
To: Frank Li; +Cc: peter.chen, gregkh, linux-usb, imx, jun.li
On Thu, Sep 12, 2024 at 01:13:54AM -0400, Frank Li wrote:
> On Thu, Sep 12, 2024 at 11:35:51AM +0800, Xu Yang wrote:
>
> usb: chipidea: udc: improve error recovery for ISO transfer
Okay.
>
> > When a endpoint met errors, the usb controller will firstly assert
> > related error bit in status filed of dTD, then ENDPTCOMPLETE will be
> > asserted. Finally, USBSTS.UEI will be set.
>
> Look like this information is not related with this patch.
I'll remove it.
>
> >
> > Due to isoc transfers are error-tolerant transfers, we can make isoc
> > endpoint a bit error tolerant on device mode too. In case of error,
> > it's possilbe to resume the endpoint by reprime the corresponding
> > endpoint.
>
> Impove device mode ISO transfer error tolerant by reprime the corresponding
> endpont.
Okay.
>
> >
> > When error occurs, this will allow error dTD be deleted from dQH and
> > giveback request to user. Then, a reprime/prime operation is executed
> > depends on whether dQH is empty or not. If dQH is not empty, reprime
> > will be done during dequeue process. If dQH is empty, prime will be
> > done when new dTD is linked. In this way, isoc transfer can be recovered
> > from a small number of errors.
>
> The recovery steps when error occurs:
> - Delete the error dTD from dQH and giveback request to user.
> - Do reprime if dQH is not empty.
> - Do prime when new dTD is queued if dQH is empty
Okay.
Thanks,
Xu Yang
>
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> > ---
> > drivers/usb/chipidea/udc.c | 12 +++++++-----
> > 1 file changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> > index 0ab57b87b07b..b1a1be6439b6 100644
> > --- a/drivers/usb/chipidea/udc.c
> > +++ b/drivers/usb/chipidea/udc.c
> > @@ -683,6 +683,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> > unsigned remaining_length;
> > unsigned actual = hwreq->req.length;
> > struct ci_hdrc *ci = hwep->ci;
> > + bool is_isoc = hwep->type == USB_ENDPOINT_XFER_ISOC;
> >
> > if (hwreq->req.status != -EALREADY)
> > return -EINVAL;
> > @@ -696,7 +697,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> > int n = hw_ep_bit(hwep->num, hwep->dir);
> >
> > if (ci->rev == CI_REVISION_24 ||
> > - ci->rev == CI_REVISION_22)
> > + ci->rev == CI_REVISION_22 || is_isoc)
> > if (!hw_read(ci, OP_ENDPTSTAT, BIT(n)))
> > reprime_dtd(ci, hwep, node);
> > hwreq->req.status = -EALREADY;
> > @@ -707,7 +708,6 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> > remaining_length >>= __ffs(TD_TOTAL_BYTES);
> > actual -= remaining_length;
> >
> > - hwreq->req.status = tmptoken & TD_STATUS;
> > if ((TD_STATUS_HALTED & hwreq->req.status)) {
> > hwreq->req.status = -EPIPE;
> > break;
> > @@ -715,11 +715,13 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> > hwreq->req.status = -EPROTO;
> > break;
> > } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
> > - hwreq->req.status = -EILSEQ;
> > - break;
> > + if (!is_isoc) {
> > + hwreq->req.status = -EILSEQ;
> > + break;
> > + }
> > }
> >
> > - if (remaining_length) {
> > + if (remaining_length && !is_isoc) {
> > if (hwep->dir == TX) {
> > hwreq->req.status = -EPROTO;
> > break;
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant
2024-09-13 1:49 ` Peter Chen
@ 2024-09-13 3:12 ` Xu Yang
0 siblings, 0 replies; 13+ messages in thread
From: Xu Yang @ 2024-09-13 3:12 UTC (permalink / raw)
To: Peter Chen; +Cc: gregkh, linux-usb, imx, jun.li
On Fri, Sep 13, 2024 at 09:49:40AM +0800, Peter Chen wrote:
> On 24-09-12 11:35:51, Xu Yang wrote:
> > When a endpoint met errors, the usb controller will firstly assert
> > related error bit in status filed of dTD, then ENDPTCOMPLETE will be
> > asserted. Finally, USBSTS.UEI will be set.
> >
> > Due to isoc transfers are error-tolerant transfers, we can make isoc
> > endpoint a bit error tolerant on device mode too. In case of error,
> > it's possilbe to resume the endpoint by reprime the corresponding
> > endpoint.
> >
> > When error occurs, this will allow error dTD be deleted from dQH and
> > giveback request to user. Then, a reprime/prime operation is executed
> > depends on whether dQH is empty or not. If dQH is not empty, reprime
> > will be done during dequeue process. If dQH is empty, prime will be
> > done when new dTD is linked. In this way, isoc transfer can be recovered
> > from a small number of errors.
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> > ---
> > drivers/usb/chipidea/udc.c | 12 +++++++-----
> > 1 file changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> > index 0ab57b87b07b..b1a1be6439b6 100644
> > --- a/drivers/usb/chipidea/udc.c
> > +++ b/drivers/usb/chipidea/udc.c
> > @@ -683,6 +683,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> > unsigned remaining_length;
> > unsigned actual = hwreq->req.length;
> > struct ci_hdrc *ci = hwep->ci;
> > + bool is_isoc = hwep->type == USB_ENDPOINT_XFER_ISOC;
> >
> > if (hwreq->req.status != -EALREADY)
> > return -EINVAL;
> > @@ -696,7 +697,7 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> > int n = hw_ep_bit(hwep->num, hwep->dir);
> >
> > if (ci->rev == CI_REVISION_24 ||
> > - ci->rev == CI_REVISION_22)
> > + ci->rev == CI_REVISION_22 || is_isoc)
> > if (!hw_read(ci, OP_ENDPTSTAT, BIT(n)))
> > reprime_dtd(ci, hwep, node);
> > hwreq->req.status = -EALREADY;
> > @@ -707,7 +708,6 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> > remaining_length >>= __ffs(TD_TOTAL_BYTES);
> > actual -= remaining_length;
> >
> > - hwreq->req.status = tmptoken & TD_STATUS;
>
> Non-ISO dTD may need error status? You may refine code by ISO and
> non-ISOC.
Oh, I have checked this line again, I indeed wrongly remove it.
I have no idea how to refine the code since they will go through
almost same path, otherwise, the code may be a bit duplicated.
Thanks,
Xu Yang
>
> Peter
>
> > if ((TD_STATUS_HALTED & hwreq->req.status)) {
> > hwreq->req.status = -EPIPE;
> > break;
> > @@ -715,11 +715,13 @@ static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
> > hwreq->req.status = -EPROTO;
> > break;
> > } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
> > - hwreq->req.status = -EILSEQ;
> > - break;
> > + if (!is_isoc) {
> > + hwreq->req.status = -EILSEQ;
> > + break;
> > + }
> > }
> >
> > - if (remaining_length) {
> > + if (remaining_length && !is_isoc) {
> > if (hwep->dir == TX) {
> > hwreq->req.status = -EPROTO;
> > break;
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set
2024-09-12 5:26 ` [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set Frank Li
@ 2024-09-13 3:21 ` Xu Yang
0 siblings, 0 replies; 13+ messages in thread
From: Xu Yang @ 2024-09-13 3:21 UTC (permalink / raw)
To: Frank Li; +Cc: peter.chen, gregkh, linux-usb, imx, jun.li
On Thu, Sep 12, 2024 at 01:26:12AM -0400, Frank Li wrote:
> On Thu, Sep 12, 2024 at 11:35:49AM +0800, Xu Yang wrote:
> > As per USBSTS register description about UEI:
> >
> > When completion of a USB transaction results in an error condition, this
> > bit is set by the Host/Device Controller. This bit is set along with the
> > USBINT bit, if the TD on which the error interrupt occurred also had its
> > interrupt on complete (IOC) bit set.
> >
> > Currently, device controller will do nothing when endpoints met transfer
> > error if IOC didn't set on that error dTD since UI didn't assert too. This
> > will also handle UEI event as same as USBSTS.UI for such cases.
>
> UI is set only when IOC set. Add checking UEI to fix miss call
> isr_tr_complete_handler() when IOC have not set and transfer error happen.
Okay.
>
> If it is user visiable issue, add fix tag and cc stable.
Okay.
>
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> > ---
> > drivers/usb/chipidea/udc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> > index 69ef3cd8d4f8..b9ccf62e0a50 100644
> > --- a/drivers/usb/chipidea/udc.c
> > +++ b/drivers/usb/chipidea/udc.c
> > @@ -2063,7 +2063,7 @@ static irqreturn_t udc_irq(struct ci_hdrc *ci)
> > }
> > }
> >
> > - if (USBi_UI & intr)
> > + if ((USBi_UI | USBi_UEI) & intr)
>
> Does it work if check UEI only?
Not work, we will lost normal USB transaction complete event.
Thanks,
Xu Yang
>
> Frank
>
> > isr_tr_complete_handler(ci);
> >
> > if ((USBi_SLI & intr) && !(ci->suspended)) {
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/3] usb: chipidea: udc: improve dTD link logic
2024-09-12 3:35 ` [PATCH 2/3] usb: chipidea: udc: improve dTD link logic Xu Yang
2024-09-12 4:54 ` Frank Li
@ 2024-09-13 8:51 ` kernel test robot
1 sibling, 0 replies; 13+ messages in thread
From: kernel test robot @ 2024-09-13 8:51 UTC (permalink / raw)
To: Xu Yang, peter.chen, gregkh; +Cc: oe-kbuild-all, linux-usb, imx, jun.li
Hi Xu,
kernel test robot noticed the following build warnings:
[auto build test WARNING on usb/usb-testing]
[also build test WARNING on usb/usb-next usb/usb-linus linus/master v6.11-rc7 next-20240912]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Xu-Yang/usb-chipidea-udc-improve-dTD-link-logic/20240912-113632
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-testing
patch link: https://lore.kernel.org/r/20240912033551.910337-2-xu.yang_2%40nxp.com
patch subject: [PATCH 2/3] usb: chipidea: udc: improve dTD link logic
config: i386-randconfig-061-20240913 (https://download.01.org/0day-ci/archive/20240913/202409131638.TJCPmqQZ-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240913/202409131638.TJCPmqQZ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202409131638.TJCPmqQZ-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/usb/chipidea/udc.c:624:33: sparse: sparse: restricted __le32 degrades to integer
vim +624 drivers/usb/chipidea/udc.c
542
543 /**
544 * _hardware_enqueue: configures a request at hardware level
545 * @hwep: endpoint
546 * @hwreq: request
547 *
548 * This function returns an error code
549 */
550 static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
551 {
552 struct ci_hdrc *ci = hwep->ci;
553 int ret = 0;
554 struct td_node *firstnode, *lastnode;
555
556 /* don't queue twice */
557 if (hwreq->req.status == -EALREADY)
558 return -EALREADY;
559
560 hwreq->req.status = -EALREADY;
561
562 ret = usb_gadget_map_request_by_dev(ci->dev->parent,
563 &hwreq->req, hwep->dir);
564 if (ret)
565 return ret;
566
567 if (hwreq->req.num_mapped_sgs)
568 ret = prepare_td_for_sg(hwep, hwreq);
569 else
570 ret = prepare_td_for_non_sg(hwep, hwreq);
571
572 if (ret)
573 return ret;
574
575 lastnode = list_entry(hwreq->tds.prev,
576 struct td_node, td);
577
578 lastnode->ptr->next = cpu_to_le32(TD_TERMINATE);
579 if (!hwreq->req.no_interrupt)
580 lastnode->ptr->token |= cpu_to_le32(TD_IOC);
581
582 list_for_each_entry_safe(firstnode, lastnode, &hwreq->tds, td)
583 trace_ci_prepare_td(hwep, hwreq, firstnode);
584
585 firstnode = list_first_entry(&hwreq->tds, struct td_node, td);
586
587 wmb();
588
589 hwreq->req.actual = 0;
590 if (!list_empty(&hwep->qh.queue)) {
591 struct ci_hw_req *hwreqprev;
592 int n = hw_ep_bit(hwep->num, hwep->dir);
593 int tmp_stat;
594 struct td_node *prevlastnode;
595 u32 next = firstnode->dma & TD_ADDR_MASK;
596
597 hwreqprev = list_entry(hwep->qh.queue.prev,
598 struct ci_hw_req, queue);
599 prevlastnode = list_entry(hwreqprev->tds.prev,
600 struct td_node, td);
601
602 prevlastnode->ptr->next = cpu_to_le32(next);
603 wmb();
604
605 if (ci->rev == CI_REVISION_22) {
606 if (!hw_read(ci, OP_ENDPTSTAT, BIT(n)))
607 reprime_dtd(ci, hwep, prevlastnode);
608 }
609
610 if (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
611 goto done;
612 do {
613 hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
614 tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n));
615 } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW) && tmp_stat);
616 hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0);
617 if (tmp_stat)
618 goto done;
619
620 /* In case of error, ENDPTSTAT will also turn into 0, then
621 * don't push this dTD to dQH head if current dTD pointer
622 * is not the last dTD in previous request.
623 */
> 624 if (hwep->qh.ptr->curr != prevlastnode->dma)
625 goto done;
626 }
627
628 /* QH configuration */
629 hwep->qh.ptr->td.next = cpu_to_le32(firstnode->dma);
630 hwep->qh.ptr->td.token &=
631 cpu_to_le32(~(TD_STATUS_HALTED|TD_STATUS_ACTIVE));
632
633 if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == RX) {
634 u32 mul = hwreq->req.length / hwep->ep.maxpacket;
635
636 if (hwreq->req.length == 0
637 || hwreq->req.length % hwep->ep.maxpacket)
638 mul++;
639 hwep->qh.ptr->cap |= cpu_to_le32(mul << __ffs(QH_MULT));
640 }
641
642 ret = hw_ep_prime(ci, hwep->num, hwep->dir,
643 hwep->type == USB_ENDPOINT_XFER_CONTROL);
644 done:
645 return ret;
646 }
647
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-09-13 8:52 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-12 3:35 [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set Xu Yang
2024-09-12 3:35 ` [PATCH 2/3] usb: chipidea: udc: improve dTD link logic Xu Yang
2024-09-12 4:54 ` Frank Li
2024-09-13 1:52 ` Xu Yang
2024-09-13 8:51 ` kernel test robot
2024-09-12 3:35 ` [PATCH 3/3] usb: chipidea: udc: make isoc endpoint a bit error tolerant Xu Yang
2024-09-12 5:13 ` Frank Li
2024-09-13 1:55 ` Xu Yang
2024-09-13 1:49 ` Peter Chen
2024-09-13 3:12 ` Xu Yang
2024-09-12 5:26 ` [PATCH 1/3] usb: chipidea: udc: handle USB Error Interrupt if IOC not set Frank Li
2024-09-13 3:21 ` Xu Yang
2024-09-13 1:37 ` Peter Chen
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox