Re: [PATCH 07/13] arm64: dts: allwinner: a100: add usb related nodes

Cody Eksal
2024-10-28T16:32:00Z

On 2024/10/25 9:44 pm, Andre Przywara wrote:
> On Thu, 24 Oct 2024 14:05:25 -0300
> Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>
> Hi,
>
>> From: Yangtao Li <frank@allwinnertech.com>
>>
>> Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
>> PHY device, let's add nodes on dts.
>>
>> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
>> [masterr3c0rd@epochal.quest: fallback to a33-musb instead of h3-musb]
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>> ---
>> .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91
>> +++++++++++++++++++
>> 1 file changed, 91 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> index adb11b26045f..0aee1b578661 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
>> @@ -302,6 +302,97 @@ ths: thermal-sensor@5070400 {
>> #thermal-sensor-cells = <1>;
>> };
>>
>> + usbphy: phy@5100400 {
>> + #phy-cells = <1>;
>
> Please keep the compatible string first, and move #phy-cells to the
> end.
Will be done in V2
>> + compatible = "allwinner,sun50i-a100-usb-phy";
>> + reg = <0x05100400 0x14>,
>> + <0x05101800 0x4>,
>> + <0x05200800 0x4>;
>
> We need at least 0x24 for the phy_ctrl and 0x14 for the PMUs. But I
> wonder if we should use 0x100 for all of them, like for the D1, as
> there
> are more registers. The fact that the Linux driver doesn't use more
> shouldn't prevent the DT from describing them.
This as well.
>> + reg-names = "phy_ctrl",
>> + "pmu0",
>> + "pmu1";
>> + clocks = <&ccu CLK_USB_PHY0>,
>> + <&ccu CLK_USB_PHY1>;
>> + clock-names = "usb0_phy",
>> + "usb1_phy";
>> + resets = <&ccu RST_USB_PHY0>,
>> + <&ccu RST_USB_PHY1>;
>> + reset-names = "usb0_reset",
>> + "usb1_reset";
>> + status = "disabled";
>> + };
>> +
>> + ehci0: usb@5101000 {
>
> The nodes are ordered by their MMIO base address, so please move them
> around accordingly.
I double checked; the only note that wasn't in order was MUSB, which
fits above the USB PHY in the memory map. I've moved those up.
>> + compatible = "allwinner,sun50i-a100-ehci",
>> + "generic-ehci";
>> + reg = <0x05101000 0x100>;
>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI0>,
>> + <&ccu CLK_BUS_EHCI0>,
>> + <&ccu CLK_USB_OHCI0>;
>> + resets = <&ccu RST_BUS_OHCI0>,
>> + <&ccu RST_BUS_EHCI0>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci0: usb@5101400 {
>> + compatible = "allwinner,sun50i-a100-ohci",
>> + "generic-ohci";
>> + reg = <0x05101400 0x100>;
>> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI0>,
>> + <&ccu CLK_USB_OHCI0>;
>> + resets = <&ccu RST_BUS_OHCI0>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + usb_otg: usb@5100000 {
>> + compatible = "allwinner,sun50i-a100-musb",
>> + "allwinner,sun8i-a33-musb";
>> + reg = <0x05100000 0x0400>;
>> + clocks = <&ccu CLK_BUS_OTG>;
>> + resets = <&ccu RST_BUS_OTG>;
>> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "mc";
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + extcon = <&usbphy 0>;
>> + dr_mode = "otg";
>
> dr_mode should be set in the board .dts, so please remove that line
> from here.
Done, and updated the Perf1 DTS to reflect this
> For the records: I checked the MMIO base addresses, clock and reset
> names and the IRQs against the manual: they all match.
Thanks again!
- Cody
> Cheers,
> Andre
>
>> + status = "disabled";
>> + };
>> +