* [PATCH] usb: dwc3: xilinx: set coherency mode for AMD versal adaptive platform
@ 2025-06-03 18:53 Radhey Shyam Pandey
2025-06-05 0:32 ` Thinh Nguyen
0 siblings, 1 reply; 2+ messages in thread
From: Radhey Shyam Pandey @ 2025-06-03 18:53 UTC (permalink / raw)
To: Thinh.Nguyen, gregkh, michal.simek
Cc: linux-usb, linux-arm-kernel, linux-kernel, git,
Radhey Shyam Pandey
If device is coherent or if DMA (direct memory access) is translated by
an IOMMU then program USB2.0 IP to route transactions through the CCI for
coherency even if the target of transaction is in low power domain (LPD).
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
---
drivers/usb/dwc3/dwc3-xilinx.c | 34 ++++++++++++++++++++++------------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index 4ca7f6240d07..00e613c4d8c0 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -32,6 +32,9 @@
#define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C
#define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1
+/* USB 2.0 IP Register */
+#define XLNX_USB2_TRAFFIC_ROUTE_CONFIG 0x0044
+
#define XLNX_USB_FPD_PIPE_CLK 0x7c
#define PIPE_CLK_DESELECT 1
#define PIPE_CLK_SELECT 0
@@ -66,6 +69,23 @@ static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
}
+static void dwc3_xlnx_set_coherency(struct dwc3_xlnx *priv_data, u32 coherency_offset)
+{
+ struct device *dev = priv_data->dev;
+ u32 reg;
+
+ /*
+ * This routes the USB DMA traffic to go through FPD path instead
+ * of reaching DDR directly. This traffic routing is needed to
+ * make SMMU and CCI work with USB DMA.
+ */
+ if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
+ reg = readl(priv_data->regs + coherency_offset);
+ reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
+ writel(reg, priv_data->regs + coherency_offset);
+ }
+}
+
static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
{
struct device *dev = priv_data->dev;
@@ -92,6 +112,7 @@ static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
}
dwc3_xlnx_mask_phy_rst(priv_data, true);
+ dwc3_xlnx_set_coherency(priv_data, XLNX_USB2_TRAFFIC_ROUTE_CONFIG);
return 0;
}
@@ -102,7 +123,6 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
struct reset_control *crst, *hibrst, *apbrst;
struct gpio_desc *reset_gpio;
int ret = 0;
- u32 reg;
priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
if (IS_ERR(priv_data->usb3_phy)) {
@@ -219,17 +239,7 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
usleep_range(5000, 10000);
}
- /*
- * This routes the USB DMA traffic to go through FPD path instead
- * of reaching DDR directly. This traffic routing is needed to
- * make SMMU and CCI work with USB DMA.
- */
- if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
- reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
- reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
- writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
- }
-
+ dwc3_xlnx_set_coherency(priv_data, XLNX_USB_TRAFFIC_ROUTE_CONFIG);
err:
return ret;
}
base-commit: a0bea9e39035edc56a994630e6048c8a191a99d8
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] usb: dwc3: xilinx: set coherency mode for AMD versal adaptive platform
2025-06-03 18:53 [PATCH] usb: dwc3: xilinx: set coherency mode for AMD versal adaptive platform Radhey Shyam Pandey
@ 2025-06-05 0:32 ` Thinh Nguyen
0 siblings, 0 replies; 2+ messages in thread
From: Thinh Nguyen @ 2025-06-05 0:32 UTC (permalink / raw)
To: Radhey Shyam Pandey
Cc: Thinh Nguyen, gregkh@linuxfoundation.org, michal.simek@amd.com,
linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, git@amd.com
On Wed, Jun 04, 2025, Radhey Shyam Pandey wrote:
> If device is coherent or if DMA (direct memory access) is translated by
> an IOMMU then program USB2.0 IP to route transactions through the CCI for
> coherency even if the target of transaction is in low power domain (LPD).
>
> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
> drivers/usb/dwc3/dwc3-xilinx.c | 34 ++++++++++++++++++++++------------
> 1 file changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
> index 4ca7f6240d07..00e613c4d8c0 100644
> --- a/drivers/usb/dwc3/dwc3-xilinx.c
> +++ b/drivers/usb/dwc3/dwc3-xilinx.c
> @@ -32,6 +32,9 @@
> #define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C
> #define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1
>
> +/* USB 2.0 IP Register */
> +#define XLNX_USB2_TRAFFIC_ROUTE_CONFIG 0x0044
> +
> #define XLNX_USB_FPD_PIPE_CLK 0x7c
> #define PIPE_CLK_DESELECT 1
> #define PIPE_CLK_SELECT 0
> @@ -66,6 +69,23 @@ static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
> writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
> }
>
> +static void dwc3_xlnx_set_coherency(struct dwc3_xlnx *priv_data, u32 coherency_offset)
> +{
> + struct device *dev = priv_data->dev;
> + u32 reg;
> +
> + /*
> + * This routes the USB DMA traffic to go through FPD path instead
> + * of reaching DDR directly. This traffic routing is needed to
> + * make SMMU and CCI work with USB DMA.
> + */
> + if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
> + reg = readl(priv_data->regs + coherency_offset);
> + reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
> + writel(reg, priv_data->regs + coherency_offset);
> + }
> +}
> +
> static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
> {
> struct device *dev = priv_data->dev;
> @@ -92,6 +112,7 @@ static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
> }
>
> dwc3_xlnx_mask_phy_rst(priv_data, true);
> + dwc3_xlnx_set_coherency(priv_data, XLNX_USB2_TRAFFIC_ROUTE_CONFIG);
>
> return 0;
> }
> @@ -102,7 +123,6 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
> struct reset_control *crst, *hibrst, *apbrst;
> struct gpio_desc *reset_gpio;
> int ret = 0;
> - u32 reg;
>
> priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
> if (IS_ERR(priv_data->usb3_phy)) {
> @@ -219,17 +239,7 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
> usleep_range(5000, 10000);
> }
>
> - /*
> - * This routes the USB DMA traffic to go through FPD path instead
> - * of reaching DDR directly. This traffic routing is needed to
> - * make SMMU and CCI work with USB DMA.
> - */
> - if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
> - reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
> - reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
> - writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
> - }
> -
> + dwc3_xlnx_set_coherency(priv_data, XLNX_USB_TRAFFIC_ROUTE_CONFIG);
> err:
> return ret;
> }
>
> base-commit: a0bea9e39035edc56a994630e6048c8a191a99d8
> --
> 2.34.1
>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
BR,
Thinh
^ permalink raw reply [flat|nested] 2+ messages in thread
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