From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D65226B955 for ; Thu, 4 Sep 2025 15:43:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757000624; cv=none; b=DHkcLlQSVVAA5ncsOAeHIi7CPod0TVNGPyQFkNZk0jd8It2EKXG0nsrN08g+F/+myhIbOhAFhpB7EvwbgZZGrFSaB5USDFDaNq7s2l5nzSmHshiXvcyl6RmjVBTDfziY1+yKzFlljbyAj0XoygEMR6/eVeY9HTCYmtNjLt4/lWg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757000624; c=relaxed/simple; bh=0gITuribvW+esoZ9lzgcYLWVym4IWPt9CFfwI6kohvc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vF0goIGb9+MAhR2P/SO9ym3offo+JTHATUh9Y/tDX5/BaMdCfjUZ29K0GBPQU8EfEQipsOOD2s2PP3Ylcgxk0sKsndTJOafYZ45Y81D0rfUm8z7zA1jOc+HU0ksZrDtTJ1be4NzTC9+bEkxicy9nUrg6l93u/FSCuaW1EtK5lIE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DpOWxUJS; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DpOWxUJS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757000621; x=1788536621; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0gITuribvW+esoZ9lzgcYLWVym4IWPt9CFfwI6kohvc=; b=DpOWxUJS1aZlKdGIS7tYlG3Lw1RcvcnMkOMTwN13idSRLV4F0sZx+4BN bZHEdsGwW1UX0M41CSpEIYon0MlzxCuGtb/XRP7xed8sDjtS4o01GitIx uyQ9kQEPfldPvGbXbM3ke/L8CgK/mkADb9i+7ExJpNq4Z8fEzJT87EBGc AKUOWksXcvhzCN5Wi1gQfvcwT8U3/cI62ZP7kuW1ytswoyg+fTlkQ1ze9 5UF/3Q5MdbTA7hxLPd3Y1lULorFglKV7Sao6y7l8j++gVAtAAvBdJeoVX hxF9bEYRaKN56vgSPP1Hakts03uVZuiGUZFB0gR5D51jl3C//xHgTY/Ox w==; X-CSE-ConnectionGUID: MnJWUGLOQW6R90CbpmRKVA== X-CSE-MsgGUID: K1O48K19TtydY3v3Syn4ww== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="63174478" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="63174478" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2025 08:43:40 -0700 X-CSE-ConnectionGUID: TY0TQGd2S52IwWGSxokulg== X-CSE-MsgGUID: yCIKE6YmQtW6RSkJBVVvCQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,238,1751266800"; d="scan'208";a="176271709" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa005.fm.intel.com with ESMTP; 04 Sep 2025 08:43:40 -0700 Received: by black.igk.intel.com (Postfix, from userid 1058) id C92F097; Thu, 04 Sep 2025 17:43:39 +0200 (CEST) From: Niklas Neronin To: mathias.nyman@linux.intel.com Cc: linux-usb@vger.kernel.org, Niklas Neronin Subject: [PATCH 5/7] usb: xhci: add USB Port Register Set struct Date: Thu, 4 Sep 2025 17:42:18 +0200 Message-ID: <20250904154221.2314596-6-niklas.neronin@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250904154221.2314596-1-niklas.neronin@linux.intel.com> References: <20250904154221.2314596-1-niklas.neronin@linux.intel.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Introduce a new struct for the Host Controller USB Port Register Set to enhance readability and maintainability. The Host Controller Operational Registers (struct 'xhci_op_regs') span from offset 0x0 to 0x3FF and consist of fixed fields. Following these fixed fields are the Host Controller USB Port Register Sets, which are dynamic and repeat from 1 to MaxPorts, as defined by HCSPARAMS1. Currently, the struct 'xhci_op_regs' includes: __le32 port_status_base; The first PORTSC __le32 port_power_base; The first PORTPMSC __le32 port_link_base; The first PORTLI __le32 reserved5; The first PORTHLPMC, not reserved __le32 reserved6[NUM_PORT_REGS*254]; Port registers 2 to MaxPorts Replace this with the simpler: struct xhci_port_regs port_regs[]; Port registers 1 to MaxPorts Host Controller USB Port Register Set: | Offset | Mnemonic | Register Name -------------------------------------------------------------------------- | 0x0 | PORTSC | Port Status and Control | 0x4 | PORTPMSC | Port Power Management Status and Control | 0x8 | PORTLI | Port Link Info | 0xC | PORTHLPMC | Port Hardware LPM Control Signed-off-by: Niklas Neronin --- drivers/usb/host/xhci-mem.c | 3 +-- drivers/usb/host/xhci.h | 36 ++++++++++++++++-------------------- 2 files changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 07289333a1e8..edd37108e5a8 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -2204,8 +2204,7 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) return -ENOMEM; for (i = 0; i < num_ports; i++) { - xhci->hw_ports[i].addr = &xhci->op_regs->port_status_base + - NUM_PORT_REGS * i; + xhci->hw_ports[i].addr = &xhci->op_regs->port_regs[i].portsc; xhci->hw_ports[i].hw_portnum = i; init_completion(&xhci->hw_ports[i].rexit_done); diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 20bc5ae3500d..5b04757325c1 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -66,14 +66,25 @@ struct xhci_cap_regs { /* Reserved up to (CAPLENGTH - 0x1C) */ }; -/* Number of registers per port */ -#define NUM_PORT_REGS 4 - #define PORTSC 0 #define PORTPMSC 1 #define PORTLI 2 #define PORTHLPMC 3 +/* + * struct xhci_port_regs - Host Controller USB Port Register Set. xHCI spec 5.4.8 + * @portsc: Port Status and Control + * @portpmsc: Port Power Management Status and Control + * @portli: Port Link Info + * @porthlmpc: Port Hardware LPM Control + */ +struct xhci_port_regs { + __le32 portsc; + __le32 portpmsc; + __le32 portli; + __le32 porthlmpc; +}; + /** * struct xhci_op_regs - xHCI Host Controller Operational Registers. * @command: USBCMD - xHC command register @@ -85,16 +96,7 @@ struct xhci_cap_regs { * @cmd_ring: CRP - 64-bit Command Ring Pointer * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer * @config_reg: CONFIG - Configure Register - * @port_status_base: PORTSCn - base address for Port Status and Control - * Each port has a Port Status and Control register, - * followed by a Port Power Management Status and Control - * register, a Port Link Info register, and a reserved - * register. - * @port_power_base: PORTPMSCn - base address for - * Port Power Management Status and Control - * @port_link_base: PORTLIn - base address for Port Link Info (current - * Link PM state and control) for USB 2.1 and USB 3.0 - * devices. + * @port_regs: Port Register Sets, from 1 to MaxPorts (defined by HCSPARAMS1). */ struct xhci_op_regs { __le32 command; @@ -110,13 +112,7 @@ struct xhci_op_regs { __le32 config_reg; /* rsvd: offset 0x3C-3FF */ __le32 reserved4[241]; - /* port 1 registers, which serve as a base address for other ports */ - __le32 port_status_base; - __le32 port_power_base; - __le32 port_link_base; - __le32 reserved5; - /* registers for ports 2-255 */ - __le32 reserved6[NUM_PORT_REGS*254]; + struct xhci_port_regs port_regs[]; }; /* USBCMD - USB command - command bitmasks */ -- 2.50.1