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[83.28.44.216]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5680c424ed5sm396292e87.4.2025.09.09.02.20.20 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 09 Sep 2025 02:20:20 -0700 (PDT) Date: Tue, 9 Sep 2025 11:20:17 +0200 From: Michal Pecio To: Niklas Neronin Cc: mathias.nyman@linux.intel.com, linux-usb@vger.kernel.org Subject: Re: [PATCH 4/7] usb: xhci: improve Endpoint Context register debugging Message-ID: <20250909112017.707158a9.michal.pecio@gmail.com> In-Reply-To: <20250903170127.2190730-5-niklas.neronin@linux.intel.com> References: <20250903170127.2190730-1-niklas.neronin@linux.intel.com> <20250903170127.2190730-5-niklas.neronin@linux.intel.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 3 Sep 2025 19:01:24 +0200, Niklas Neronin wrote: > Improve the debugging output for Endpoint Context registers in the xHCI > driver. The Endpoint Context registers consist of the following fields: > bit 0 - Dequeue Cycle State. > bits 3:1 - RsvdZ. > bits 63:4 - TR Dequeue Pointer, is 16-byte aligned. > > Instead of printing the entire 64-bit register as a single block, each > field is now printed separately. This approach enhances the readability. > > xHCI specification, section 6.2.3. > > Why not use 'dma_addr_t' for the address? > The 'dma_addr_t' type can vary between 32 and 64 bits depending on the > system architecture or xHCI driver flags, whereas the 64-bit address field > size remains constant. Since hardware cannot be fully trusted, it's better > to print the entire 64-bit address to detect any non-zero values in the > upper 32 bits. This approach ensures that potential issues are easily > detected. > > Signed-off-by: Niklas Neronin > --- > drivers/usb/host/xhci.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h > index 59ff84ba2d4a..2662356d048e 100644 > --- a/drivers/usb/host/xhci.h > +++ b/drivers/usb/host/xhci.h > @@ -2580,9 +2580,9 @@ static inline const char *xhci_decode_ep_context(char *str, u32 info, > ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", > (1 << interval) * 125, esit, cerr); > > - ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", > + ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx cycle %llu", > xhci_ep_type_string(ep_type), hid ? "HID" : "", > - burst, maxp, deq); > + burst, maxp, deq & TR_DEQ_PTR_MASK, deq & EP_CTX_CYCLE_MASK); Does it really bother people who use debugfs that deq includes the cycle bit, which is exactly what anyone who know xHCI will expect? This line is quite damn long already. Also, I am highly confident that you haven't even tested this patch. Try it and see what happens ;) > > ret += sprintf(str + ret, "avg trb len %d", avg); > > -- > 2.50.1 >