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Sun, 02 Nov 2025 08:48:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IG4nhNS7nlqb2YAi5SG0s0Ji9IjMUZXRJ64Vy+PMlEEPlTIQJRkSfTGlck3/uwqMo4IbTmG2g== X-Received: by 2002:a05:6a21:999c:b0:2e3:a914:aab7 with SMTP id adf61e73a8af0-348cc6ed95bmr12421562637.47.1762102116700; Sun, 02 Nov 2025 08:48:36 -0800 (PST) Received: from hu-kriskura-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b93bda55f74sm7708125a12.19.2025.11.02.08.48.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Nov 2025 08:48:36 -0800 (PST) From: Krishna Kurapati To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Biju Das , Dmitry Baryshkov Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krishna Kurapati Subject: [PATCH v6 2/2] usb: typec: hd3ss3220: Enable VBUS based on ID pin state Date: Sun, 2 Nov 2025 22:18:19 +0530 Message-Id: <20251102164819.2798754-3-krishna.kurapati@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251102164819.2798754-1-krishna.kurapati@oss.qualcomm.com> References: <20251102164819.2798754-1-krishna.kurapati@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=StidKfO0 c=1 sm=1 tr=0 ts=69078b66 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=3eHL1KmHa9FwJ4YL2wMA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: RNMhHaXnxnmjguialt5CWdOW5sB_Bos6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTAyMDE1NiBTYWx0ZWRfXxRnti3guwSad Fed2a1kS1baWzk18KAwf2tWhpxyqb1fq4GAIxiTWohauqqwZARWtH3IeXc4KOSoU5HsEyCDv0KC eyXACGKfvC+IZpRofX6010iVWbyQxwaRVX2yqAPA+1+VyAkhATX0XkPtMSAPsRnG6OXMj2gg8JZ EV0G51dpePU0faVyh/yluzaHG4ThYUOvnuJZ0oLSWrV92/PXAlPRzQbbDBi9/lw6Dz7LmCDt7MG Tcsh+4RyOwWJ6ZOrm3RebAtGiYPLxyEiIZZZVze+x1VGE4uuIxv/HcgvHe24oCIAyhB1dVgOfT4 +dGrxqdO3W2cx/QGG4zEmAolssq3ilJ/cZ3XHl89jGNkdVJK63LxfAMlcQciFO5NDzVcPk/krrd iijCsxdZr+0r74ta38s+mwxk0emjuQ== X-Proofpoint-ORIG-GUID: RNMhHaXnxnmjguialt5CWdOW5sB_Bos6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-02_02,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 adultscore=0 malwarescore=0 impostorscore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511020156 There is a ID pin present on HD3SS3220 controller that can be routed to SoC. As per the datasheet: "Upon detecting a UFP device, HD3SS3220 will keep ID pin high if VBUS is not at VSafe0V. Once VBUS is at VSafe0V, the HD3SS3220 will assert ID pin low. This is done to enforce Type-C requirement that VBUS must be at VSafe0V before re-enabling VBUS" Add support to read the ID pin state and enable VBUS accordingly. Signed-off-by: Krishna Kurapati --- drivers/usb/typec/hd3ss3220.c | 72 +++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/usb/typec/hd3ss3220.c b/drivers/usb/typec/hd3ss3220.c index 3ecc688dda82..75fbda42eaf4 100644 --- a/drivers/usb/typec/hd3ss3220.c +++ b/drivers/usb/typec/hd3ss3220.c @@ -15,6 +15,9 @@ #include #include #include +#include +#include +#include #define HD3SS3220_REG_CN_STAT 0x08 #define HD3SS3220_REG_CN_STAT_CTRL 0x09 @@ -54,6 +57,11 @@ struct hd3ss3220 { struct delayed_work output_poll_work; enum usb_role role_state; bool poll; + + struct gpio_desc *id_gpiod; + int id_irq; + + struct regulator *vbus; }; static int hd3ss3220_set_power_opmode(struct hd3ss3220 *hd3ss3220, int power_opmode) @@ -319,6 +327,44 @@ static const struct regmap_config config = { .max_register = 0x0A, }; +static irqreturn_t hd3ss3220_id_isr(int irq, void *dev_id) +{ + struct hd3ss3220 *hd3ss3220 = dev_id; + int ret; + int id; + + if (!hd3ss3220->vbus) + return IRQ_HANDLED; + + id = hd3ss3220->id_gpiod ? gpiod_get_value_cansleep(hd3ss3220->id_gpiod) : 1; + + if (!id) { + ret = regulator_enable(hd3ss3220->vbus); + if (ret) + dev_err(hd3ss3220->dev, "enable vbus regulator failed\n"); + } else { + regulator_disable(hd3ss3220->vbus); + } + + return IRQ_HANDLED; +} + +static int hd3ss3220_get_vbus_supply(struct hd3ss3220 *hd3ss3220, + struct fwnode_handle *connector) +{ + int ret = 0; + + hd3ss3220->vbus = devm_of_regulator_get_optional(hd3ss3220->dev, + to_of_node(connector), + "vbus"); + if (PTR_ERR(hd3ss3220->vbus) == -ENODEV) + hd3ss3220->vbus = NULL; + else if (IS_ERR(hd3ss3220->vbus)) + ret = PTR_ERR(hd3ss3220->vbus); + + return ret; +} + static int hd3ss3220_probe(struct i2c_client *client) { struct typec_capability typec_cap = { }; @@ -354,11 +400,37 @@ static int hd3ss3220_probe(struct i2c_client *client) hd3ss3220->role_sw = usb_role_switch_get(hd3ss3220->dev); } + hd3ss3220->id_gpiod = devm_gpiod_get_optional(hd3ss3220->dev, "id", GPIOD_IN); + if (IS_ERR(hd3ss3220->id_gpiod)) + return PTR_ERR(hd3ss3220->id_gpiod); + + if (hd3ss3220->id_gpiod) { + hd3ss3220->id_irq = gpiod_to_irq(hd3ss3220->id_gpiod); + if (hd3ss3220->id_irq < 0) + return dev_err_probe(hd3ss3220->dev, hd3ss3220->id_irq, + "failed to get ID gpio\n"); + + ret = devm_request_threaded_irq(hd3ss3220->dev, + hd3ss3220->id_irq, NULL, + hd3ss3220_id_isr, + IRQF_TRIGGER_RISING | + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + dev_name(hd3ss3220->dev), hd3ss3220); + if (ret < 0) + return dev_err_probe(hd3ss3220->dev, ret, "failed to get ID irq\n"); + } + if (IS_ERR(hd3ss3220->role_sw)) { ret = PTR_ERR(hd3ss3220->role_sw); goto err_put_fwnode; } + ret = hd3ss3220_get_vbus_supply(hd3ss3220, connector); + if (ret) { + dev_err(hd3ss3220->dev, "failed to get vbus: %d\n", ret); + goto err_put_fwnode; + } + typec_cap.prefer_role = TYPEC_NO_PREFERRED_ROLE; typec_cap.driver_data = hd3ss3220; typec_cap.type = TYPEC_PORT_DRP; -- 2.34.1