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From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Atharva Tiwari <atharvatiwarilinuxdev@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
	Oliver O'Halloran <oohall@gmail.com>,
	Andreas Noever <andreas.noever@gmail.com>,
	Mika Westerberg <westeri@kernel.org>,
	Yehezkel Bernat <YehezkelShB@gmail.com>,
	Lukas Wunner <lukas@wunner.de>,
	Kuppuswamy Sathyanarayanan
	<sathyanarayanan.kuppuswamy@linux.intel.com>,
	Feng Tang <feng.tang@linux.alibaba.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linuxppc-dev@lists.ozlabs.org, linux-usb@vger.kernel.org
Subject: Re: [PATCH v4] PCI/portdev: Disable AER for Titan Ridge 4C 2018
Date: Thu, 8 Jan 2026 10:53:03 +0100	[thread overview]
Message-ID: <20260108095303.GQ2275908@black.igk.intel.com> (raw)
In-Reply-To: <20260108082509.3028-1-atharvatiwarilinuxdev@gmail.com>

On Thu, Jan 08, 2026 at 08:25:03AM +0000, Atharva Tiwari wrote:
> Disable AER for Intel Titan Ridge 4C 2018
> (used in T2 iMacs, where the warnings appear)
> that generate continuous pcieport warnings. such as:

Did you try the v6.19-rcX as Lukas suggested? What was the result?

I asked also to provide full dmesg and 'sudo lspci -vv' output but you did
not provide them. You also did not provide details of what device you
connect to this system.

It would be good to try to understand what is going on before we add any
quirks.

> pcieport 0000:00:1c.4: AER: Correctable error message received from 0000:07:00.0
> pcieport 0000:07:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Receiver ID)
> pcieport 0000:07:00.0:   device [8086:15ea] error status/mask=00000080/00002000
> pcieport 0000:07:00.0:    [ 7] BadDLLP
> 
> macOS also disables AER for Thunderbolt devices and controllers in their drivers.
> 
> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=220651
> Signed-off-by: Atharva Tiwari <atharvatiwarilinuxdev@gmail.com>
> 
> ---
> Chnages since v3:
> - Fixed Grammer mistakes
> Changes since v2:
> - Transferred logic to arch/x86/pci/fixup.c to only target x86
> - Added DMI quirk to only target Apple Systems
> Changes since v1:
> - Transferred logic to drivers/pci/quicks.c
> ---
> ---
>  arch/x86/pci/fixup.c       | 12 ++++++++++++
>  drivers/pci/pcie/aer.c     |  3 +++
>  drivers/pci/pcie/portdrv.c |  2 +-
>  include/linux/pci.h        |  1 +
>  4 files changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
> index 25076a5acd96..bd72f7cf5db9 100644
> --- a/arch/x86/pci/fixup.c
> +++ b/arch/x86/pci/fixup.c
> @@ -1081,3 +1081,15 @@ static void quirk_tuxeo_rp_d3(struct pci_dev *pdev)
>  }
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1502, quirk_tuxeo_rp_d3);
>  #endif /* CONFIG_SUSPEND */
> +
> +#ifdef CONFIG_PCIEAER
> +
> +static void quirk_disable_aer(struct pci_dev *pdev)
> +{
> +	if (dmi_match(DMI_SYS_VENDOR, "Apple"))
> +		pdev->no_aer = 1;
> +}
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x15EA, quirk_disable_aer);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x15EB, quirk_disable_aer);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x15EC, quirk_disable_aer);

Use small letters in hex: 0x15ea etc.

> +#endif /* CONFIG_PCIEAER */
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index e0bcaa896803..45604564ce6f 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -389,6 +389,9 @@ void pci_aer_init(struct pci_dev *dev)
>  {
>  	int n;
>  
> +	if (dev->no_aer)
> +		return;
> +
>  	dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
>  	if (!dev->aer_cap)
>  		return;
> diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c
> index 38a41ccf79b9..ab904a224296 100644
> --- a/drivers/pci/pcie/portdrv.c
> +++ b/drivers/pci/pcie/portdrv.c
> @@ -240,7 +240,7 @@ static int get_port_device_capability(struct pci_dev *dev)
>  	if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
>               pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) &&
>  	    dev->aer_cap && pci_aer_available() &&
> -	    (pcie_ports_native || host->native_aer))
> +	    (pcie_ports_native || host->native_aer) && !dev->no_aer)
>  		services |= PCIE_PORT_SERVICE_AER;
>  #endif
>  
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 864775651c6f..f447f86c6bdf 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -440,6 +440,7 @@ struct pci_dev {
>  	unsigned int	multifunction:1;	/* Multi-function device */
>  
>  	unsigned int	is_busmaster:1;		/* Is busmaster */
> +	unsigned int	no_aer:1;		/* May not use AER */
>  	unsigned int	no_msi:1;		/* May not use MSI */
>  	unsigned int	no_64bit_msi:1;		/* May only use 32-bit MSIs */
>  	unsigned int	block_cfg_access:1;	/* Config space access blocked */
> -- 
> 2.43.0

  reply	other threads:[~2026-01-08  9:53 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-08  8:25 [PATCH v4] PCI/portdev: Disable AER for Titan Ridge 4C 2018 Atharva Tiwari
2026-01-08  9:53 ` Mika Westerberg [this message]
2026-01-08 10:33   ` Atharva Tiwari
2026-01-08 11:37     ` Mika Westerberg
2026-01-08 14:18       ` Atharva Tiwari
2026-01-09  6:57         ` Mika Westerberg
2026-01-09  8:14           ` Atharva Tiwari
2026-01-09 10:08             ` Mika Westerberg
2026-01-09 11:06               ` Atharva Tiwari
2026-01-08 10:37   ` Atharva Tiwari

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