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From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: "Chia-Lin Kao (AceLan)" <acelan.kao@canonical.com>,
	Andreas Noever <andreas.noever@gmail.com>,
	Mika Westerberg <westeri@kernel.org>,
	Yehezkel Bernat <YehezkelShB@gmail.com>,
	linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] thunderbolt: Fix PCIe device enumeration with delayed rescan
Date: Mon, 26 Jan 2026 12:56:54 +0100	[thread overview]
Message-ID: <20260126115654.GS2275908@black.igk.intel.com> (raw)
In-Reply-To: <aXcWNw9Qfo5L9WVi@acelan-Precision-5480>

On Mon, Jan 26, 2026 at 03:48:48PM +0800, Chia-Lin Kao (AceLan) wrote:
> On Mon, Jan 26, 2026 at 06:42:31AM +0100, Mika Westerberg wrote:
> > On Mon, Jan 26, 2026 at 11:30:47AM +0800, Chia-Lin Kao (AceLan) wrote:
> > > Hi,
> > > On Fri, Jan 23, 2026 at 01:01:12PM +0100, Mika Westerberg wrote:
> > > > Hi,
> > > >
> > > > On Fri, Jan 23, 2026 at 10:04:11AM +0800, Chia-Lin Kao (AceLan) wrote:
> > > > > > Can you comment out call to tb_switch_xhci_connect() and see if that
> > > > > > changes anything?
> > > > >
> > > > > Here is what I modified, and the problem becomes a little bit complicated.
> > > >
> > > > Okay I see it did not change anything (well this is kind of what I
> > > > expected). Thanks for trying.
> > > >
> > > > I see in your log that the PCIe tunnel is established just fine. It's just
> > > > that there is no PCIe hotplug happening or it is happening but the PCIe
> > > > Downstream Port is not waking up.
> > > >
> > > > I figured you have following USB4/TB topology, right?
> > > >
> > > >   AMD Host <-> GR Hub <-> TB3 Hub
> > > >                   ^
> > > >                   |
> > > >                 TB3 Hub
> > > Should be more like this
> > >   AMD Host <-> Dell TB4 Dock <-> OWC Envoy Express (1-502)
> > >                              \
> > >                               <-> OWC Envoy Express (1-702)
> > > or
> > >   AMD Host (1-0, domain1)
> > >       |
> > >       └─ Port 2 ──→ Dell Thunderbolt 4 Dock (1-2)
> > >                       ├─ Port 5 ──→ OWC Envoy Express (1-502)
> > >                       └─ Port 7 ──→ OWC Envoy Express (1-702)
> >
> > Okay so the same ;-)
> >
> > > > What if you run 'lspci' after the issue reproduces? Does that bring the
> > > > missing PCIe devices? I suspect that this is due to older TB3 devices that
> > > > they may need bit more time to get the PCIe link (going over the tunnel) up
> > > > and running.
> > > lspci doesn't bring back the missing tbt storage.
> >
> > Forgot to mention that let it (the whole topology) enter runtime suspend
> > before you run lspci.
> 
> https://people.canonical.com/~acelan/bugs/tbt_storage/dmesg_lspci.log
> 
> The behavior is strange, the following 3 devices keep entering D3cold and then comes back
> to D0 quickly. So, I'm not sure if the lspci do the actions you want.

Yes. I should have mentioned so the lspci is there exactly to trigger
runtime resume of the topology. I was hoping the PCIe links get
re-established properly then.

Can you do so that you:

1. Plug in the dock.
2. Plug in the other storage to the dock.
3. Block runtime PM from the PCIe Downstream Port that should lead to the
   second storage device PCIe Upstream Port

 # echo on > /sys/bus/pci/devices/DEVICE/power/control

4. Connect the second storage device and enable PCIe tunnel.

Does that make it work each time?

  parent reply	other threads:[~2026-01-26 11:56 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-21  5:27 [PATCH] thunderbolt: Fix PCIe device enumeration with delayed rescan Chia-Lin Kao (AceLan)
2026-01-21  5:35 ` AceLan Kao
2026-01-21  6:01 ` Mika Westerberg
2026-01-23  2:04   ` Chia-Lin Kao (AceLan)
2026-01-23 12:01     ` Mika Westerberg
     [not found]       ` <aXbTfLUJ-lEfNzgX@acelan-Precision-5480>
2026-01-26  5:42         ` Mika Westerberg
     [not found]           ` <aXcWNw9Qfo5L9WVi@acelan-Precision-5480>
2026-01-26 11:56             ` Mika Westerberg [this message]
     [not found]               ` <aXg1eBudRAaCZpmR@acelan-Precision-5480>
2026-01-27  8:45                 ` Mika Westerberg
2026-01-27 10:17                   ` Mika Westerberg
2026-01-29  5:45                     ` Chia-Lin Kao (AceLan)
2026-01-29  6:50                       ` Mika Westerberg
2026-02-03  9:04                         ` Jayi Li
2026-02-03  9:39                           ` Mika Westerberg
2026-02-03 10:00                             ` Jayi Li
2026-02-03 10:07                               ` Mika Westerberg
2026-02-04  2:37                                 ` Jayi Li
2026-02-04 12:37                                   ` Mika Westerberg
2026-02-06  1:17                                     ` Jayi Li
2026-02-09  1:30                                     ` Jayi Li
2026-02-12  4:16                         ` AceLan Kao
2026-02-12  7:07                           ` Mika Westerberg
2026-02-12  7:34                             ` Mika Westerberg
2026-02-13  0:34                               ` Mario Limonciello
2026-02-18 19:21                                 ` Mario Limonciello
2026-02-18 21:35                                   ` Mario Limonciello
2026-02-23  5:55                                     ` Mika Westerberg

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