From: Gil Fine <gil.fine@linux.intel.com>
To: andreas.noever@gmail.com, mika.westerberg@linux.intel.com,
YehezkelShB@gmail.com
Cc: gil.fine@intel.com, linux-usb@vger.kernel.org, lukas@wunner.de,
Gil Fine <gil.fine@linux.intel.com>
Subject: [PATCH 1/5] thunderbolt: Fix lane bonding log message when bonding not possible
Date: Tue, 27 Jan 2026 00:06:02 +0200 [thread overview]
Message-ID: <20260126220606.3476657-2-gil.fine@linux.intel.com> (raw)
In-Reply-To: <20260126220606.3476657-1-gil.fine@linux.intel.com>
Currently, if lane bonding is not possible or not supported, we continue
and read the updated number of Total Buffers from lane adapters without need,
and incorrectly log the bonding flow as succeeded even if it didn't.
Fix lane bonding log message when bonding not possible and bail out early.
Signed-off-by: Gil Fine <gil.fine@linux.intel.com>
---
drivers/thunderbolt/switch.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index dda30e1d75e9..e7faa203b782 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -2953,14 +2953,14 @@ static int tb_switch_lane_bonding_enable(struct tb_switch *sw)
int ret;
if (!tb_switch_lane_bonding_possible(sw))
- return 0;
+ return -EOPNOTSUPP;
up = tb_upstream_port(sw);
down = tb_switch_downstream_port(sw);
if (!tb_port_width_supported(up, TB_LINK_WIDTH_DUAL) ||
!tb_port_width_supported(down, TB_LINK_WIDTH_DUAL))
- return 0;
+ return -EOPNOTSUPP;
/*
* Both lanes need to be in CL0. Here we assume lane 0 already be in
--
2.43.0
next prev parent reply other threads:[~2026-01-26 22:02 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-26 22:06 [PATCH 0/5] CM fixes to follow CM guide more closely Gil Fine
2026-01-26 22:06 ` Gil Fine [this message]
2026-01-26 22:06 ` [PATCH 2/5] thunderbolt: Verify PCIe adapters in detect state before setup PCIe tunnel Gil Fine
2026-01-27 9:49 ` Mika Westerberg
2026-01-26 22:06 ` [PATCH 3/5] thunderbolt: Verify Router Ready bit is set after router enumeration Gil Fine
2026-01-27 9:53 ` Mika Westerberg
2026-01-26 22:06 ` [PATCH 4/5] thunderbolt: Increase timeout to wait for Configuration Ready bit Gil Fine
2026-01-26 22:06 ` [PATCH 5/5] thunderbolt: Increase Notification Timeout to 255 ms for USB4 routers Gil Fine
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