From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Gil Fine <gil.fine@linux.intel.com>
Cc: andreas.noever@gmail.com, YehezkelShB@gmail.com,
gil.fine@intel.com, linux-usb@vger.kernel.org, lukas@wunner.de
Subject: Re: [PATCH 2/5] thunderbolt: Verify PCIe adapters in detect state before setup PCIe tunnel
Date: Tue, 27 Jan 2026 10:49:53 +0100 [thread overview]
Message-ID: <20260127094953.GF2275908@black.igk.intel.com> (raw)
In-Reply-To: <20260126220606.3476657-3-gil.fine@linux.intel.com>
On Tue, Jan 27, 2026 at 12:06:03AM +0200, Gil Fine wrote:
> USB4 Connection Manager guide suggests making sure PCIe downstream and PCIe
> upstream adapter is in Detect state, before set up a PCIe tunnel.
>
> Add this step by checking LTSSM field in ADP_PCIE_CS_0 to follow the CM
> guide more closely.
>
> Signed-off-by: Gil Fine <gil.fine@linux.intel.com>
> ---
> drivers/thunderbolt/tb.h | 2 ++
> drivers/thunderbolt/tb_regs.h | 15 +++++++++++++++
> drivers/thunderbolt/tunnel.c | 17 +++++++++++++++++
> drivers/thunderbolt/usb4.c | 23 +++++++++++++++++++++++
> 4 files changed, 57 insertions(+)
>
> diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
> index c2ff2069eb20..dbbbd2bd63f3 100644
> --- a/drivers/thunderbolt/tb.h
> +++ b/drivers/thunderbolt/tb.h
> @@ -1480,6 +1480,8 @@ int usb4_dp_port_allocate_bandwidth(struct tb_port *port, int bw);
> int usb4_dp_port_requested_bandwidth(struct tb_port *port);
>
> int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable);
> +int usb4_pci_port_check_ltssm_state(struct tb_port *port,
> + enum tb_pcie_ltssm_state ltssm);
>
> static inline bool tb_is_usb4_port_device(const struct device *dev)
> {
> diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h
> index c0bf136236e6..71bed02a6974 100644
> --- a/drivers/thunderbolt/tb_regs.h
> +++ b/drivers/thunderbolt/tb_regs.h
> @@ -473,10 +473,25 @@ struct tb_regs_port_header {
>
> /* PCIe adapter registers */
> #define ADP_PCIE_CS_0 0x00
> +#define ADP_PCIE_CS_0_LTSSM_MASK GENMASK(28, 25)
> #define ADP_PCIE_CS_0_PE BIT(31)
> #define ADP_PCIE_CS_1 0x01
> #define ADP_PCIE_CS_1_EE BIT(0)
>
> +enum tb_pcie_ltssm_state {
> + TB_PCIE_LTSSM_DETECT = 0x0,
> + TB_PCIE_LTSSM_POLLING = 0x1,
> + TB_PCIE_LTSSM_CONFIG = 0x2,
> + TB_PCIE_LTSSM_CONFIG_IDLE = 0x3,
> + TB_PCIE_LTSSM_RECOVERY = 0x4,
> + TB_PCIE_LTSSM_RECOVERY_IDLE = 0x5,
> + TB_PCIE_LTSSM_L0 = 0x6,
> + TB_PCIE_LTSSM_L1 = 0x7,
> + TB_PCIE_LTSSM_L2 = 0x8,
> + TB_PCIE_LTSSM_DISABLED = 0x9,
> + TB_PCIE_LTSSM_HOT_RESET = 0xa,
> +};
> +
> /* USB adapter registers */
> #define ADP_USB3_CS_0 0x00
> #define ADP_USB3_CS_0_V BIT(30)
> diff --git a/drivers/thunderbolt/tunnel.c b/drivers/thunderbolt/tunnel.c
> index 28c1e5c062f3..72beaf99765f 100644
> --- a/drivers/thunderbolt/tunnel.c
> +++ b/drivers/thunderbolt/tunnel.c
> @@ -296,6 +296,22 @@ static inline void tb_tunnel_changed(struct tb_tunnel *tunnel)
> tunnel->src_port, tunnel->dst_port);
> }
>
> +static int tb_pci_pre_activate(struct tb_tunnel *tunnel)
> +{
> + struct tb_port *down = tunnel->src_port;
> + struct tb_port *up = tunnel->dst_port;
> + int ret;
> +
> + if (!tb_switch_is_usb4(down->sw) || !tb_switch_is_usb4(up->sw))
What if
USB4 <-> TB3
I think we should do the same still, no?
> + return 0;
> +
> + ret = usb4_pci_port_check_ltssm_state(down, TB_PCIE_LTSSM_DETECT);
> + if (ret)
> + return ret;
> +
> + return usb4_pci_port_check_ltssm_state(up, TB_PCIE_LTSSM_DETECT);
> +}
> +
> static int tb_pci_set_ext_encapsulation(struct tb_tunnel *tunnel, bool enable)
> {
> struct tb_port *port = tb_upstream_port(tunnel->dst_port->sw);
> @@ -511,6 +527,7 @@ struct tb_tunnel *tb_tunnel_alloc_pci(struct tb *tb, struct tb_port *up,
> if (!tunnel)
> return NULL;
>
> + tunnel->pre_activate = tb_pci_pre_activate;
> tunnel->activate = tb_pci_activate;
> tunnel->src_port = down;
> tunnel->dst_port = up;
> diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c
> index 403a46aa35e5..706c9bc796e2 100644
> --- a/drivers/thunderbolt/usb4.c
> +++ b/drivers/thunderbolt/usb4.c
> @@ -3145,3 +3145,26 @@ int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
> return tb_port_write(port, &val, TB_CFG_PORT,
> port->cap_adap + ADP_PCIE_CS_1, 1);
> }
> +
> +/**
> + * usb4_pci_port_check_ltssm_state() - Checks the LTSSM state of PCIe adapter
> + * @port: PCIe adapter
> + * @ltssm: PCIe adapter LTSSM state as encoded in &enum tb_pcie_ltssm_state
> + *
> + * Return:
> + * * %0 - If LTSSM state of @port is as expected @state.
> + * * %-ETIMEDOUT - The @ltssm state was not reached within the given timeout.
> + * * Negative errno - Other failure occurred.
> + */
> +int usb4_pci_port_check_ltssm_state(struct tb_port *port,
> + enum tb_pcie_ltssm_state ltssm)
> +{
> + u32 val = FIELD_PREP(ADP_PCIE_CS_0_LTSSM_MASK, ltssm);
> +
> + if (!tb_port_is_pcie_down(port) && !tb_port_is_pcie_up(port))
> + return -EINVAL;
> +
> + return usb4_port_wait_for_bit(port, port->cap_adap + ADP_PCIE_CS_0,
> + ADP_PCIE_CS_0_LTSSM_MASK, val, 500,
> + USB4_PORT_DELAY);
> +}
> --
> 2.43.0
next prev parent reply other threads:[~2026-01-27 9:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-26 22:06 [PATCH 0/5] CM fixes to follow CM guide more closely Gil Fine
2026-01-26 22:06 ` [PATCH 1/5] thunderbolt: Fix lane bonding log message when bonding not possible Gil Fine
2026-01-26 22:06 ` [PATCH 2/5] thunderbolt: Verify PCIe adapters in detect state before setup PCIe tunnel Gil Fine
2026-01-27 9:49 ` Mika Westerberg [this message]
2026-01-26 22:06 ` [PATCH 3/5] thunderbolt: Verify Router Ready bit is set after router enumeration Gil Fine
2026-01-27 9:53 ` Mika Westerberg
2026-01-26 22:06 ` [PATCH 4/5] thunderbolt: Increase timeout to wait for Configuration Ready bit Gil Fine
2026-01-26 22:06 ` [PATCH 5/5] thunderbolt: Increase Notification Timeout to 255 ms for USB4 routers Gil Fine
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