Re: [PATCH] usb: dwc3: Support for USB3340x ULPI PHY, via "snps,enable_xcvrdly_quirk"

[Thinh Nguyen <Thinh.Nguyen@synopsys.com>]

On Tue, Feb 24, 2026, Ingo Rohloff wrote:
> The Microchip USB3340x ULPI PHY requires a delay when switching to the
> high-speed transmitter.
> 
> Original description is/was in Xilinx Wiki under
> "USB Debug Guide for Zynq UltraScale+ and Versal Devices"
> 
> Signed-off-by: Ingo Rohloff <ingo.rohloff@lauterbach.com>
> ---
>  drivers/usb/dwc3/core.c | 20 ++++++++++++++++++++
>  drivers/usb/dwc3/core.h |  2 ++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 161a4d58b2ce..92ad701a9340 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -777,6 +777,23 @@ static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
>  	if (dwc->ulpi_ext_vbus_drv)
>  		reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
>  
> +	/*
> +	 * Fixes High-speed negotiation issue with USB3340, see:
> +	 *    https://urldefense.com/v3/__http://ww1.microchip.com/downloads/en/DeviceDoc/80000645A.pdf__;!!A4F2R9G_pg!dXav8YHma6OhZWR1jhFvBxM4Wgv7OAUPjMgBS8CRz-P0x2OTr8PGbErUg7RtcbLfsNihsPay4lHdvoLJnN9nJoxGJqwb2qg$ 
> +	 *    "Device Enumeration Failure with Link IP Systems"

This platform specific info and how it was found should go into the
commit message and not here.

> +	 * According to documentation on the Internet,

We should not just reference the "Internet". If you want to reference
some documentation, please provide the DWC_usb3x document section and
version.

> +	 * DWC3_GUSB2PHYCFG_XCVRDLY:
> +	 *    Adds a delay between the assertion of the
> +	 *    ULPI Transceiver Select signal (for HS) and

It can be for both ULPI and UTMI.

> +	 *    the assertion of the TxValid signal during a HS Chirp.
> +	 *
> +	 * This bit also needs to be set again when the device comes out
> +	 * of hibernation, this is currently not an issue since hibernation
> +	 * is not enabled.
> +	 */

IMO, this doc should go in the commit message.

> +	if (dwc->enable_xcvrdly_quirk)
> +		reg |= DWC3_GUSB2PHYCFG_XCVRDLY;
> +
>  	dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg);
>  
>  	return 0;
> @@ -1855,6 +1872,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
>  	dwc->dis_split_quirk = device_property_read_bool(dev,
>  				"snps,dis-split-quirk");
>  
> +	dwc->enable_xcvrdly_quirk = device_property_read_bool(dev,
> +				"snps,enable_xcvrdly_quirk");

Use "-" instead of "_" for property name, and change it to
"snps,enable-usb2-transceiver-delay"

Also, how are you passing this quirk? Through devicetree or software
node? I don't see the user of this property.

> +
>  	dwc->lpm_nyet_threshold = lpm_nyet_threshold;
>  	dwc->tx_de_emphasis = tx_de_emphasis;
>  
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index a35b3db1f9f3..41418f3f85e1 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -302,6 +302,7 @@
>  #define DWC3_GUSB2PHYCFG_SUSPHY		BIT(6)
>  #define DWC3_GUSB2PHYCFG_ULPI_UTMI	BIT(4)
>  #define DWC3_GUSB2PHYCFG_ENBLSLPM	BIT(8)
> +#define DWC3_GUSB2PHYCFG_XCVRDLY	BIT(9)
>  #define DWC3_GUSB2PHYCFG_PHYIF(n)	(n << 3)
>  #define DWC3_GUSB2PHYCFG_PHYIF_MASK	DWC3_GUSB2PHYCFG_PHYIF(1)
>  #define DWC3_GUSB2PHYCFG_USBTRDTIM(n)	(n << 10)
> @@ -1403,6 +1404,7 @@ struct dwc3 {
>  	unsigned		dis_metastability_quirk:1;
>  
>  	unsigned		dis_split_quirk:1;
> +	unsigned		enable_xcvrdly_quirk:1;

Document the new field. Rename to enable_usb2_transceiver_delay.

>  	unsigned		async_callbacks:1;
>  	unsigned		sys_wakeup:1;
>  	unsigned		wakeup_configured:1;
> -- 
> 2.52.0
> 

BR,
Thinh