Re: [PATCH] usb: dwc3: Support for USB3340x ULPI PHY, via "snps,enable_xcvrdly_quirk"

[Ingo Rohloff <ingo.rohloff@lauterbach.com>]

Hello Thinh,

On Thu, 26 Feb 2026 02:39:46 +0000
Thinh Nguyen <Thinh.Nguyen@synopsys.com> wrote:

> > > Also, how are you passing this quirk? Through devicetree or software
> > > node? I don't see the user of this property.
> > >   
> > 
> > On the hardware I have got (Xilinx Ultrascale+ ZynqMP) I pass it via
> > devicetree. I now added a 2nd commit, which adds documentation for the
> > devicetree bindings.
> >   
> 
> You should pass this via software node through the glue driver. I don't
> think there's enough justification to create a new devicetree property
> just for this.

Please help me to understand:
I think the glue driver you are referring to is the Xilinix specific one,
so the one in `drivers/usb/dwc3/dwc3-xilinx.c`, which declares
`dwc3_xlnx_driver`.

Is this what you mean?

I think I understand how to create a software node there and how to pass
it to the main dwc3 driver.

Do you mean to read in a dwc3_xlnx_driver specific device tree property
and then pass this via software node to the main DWC3 driver?

I am wondering if the dwc3_xlnx_driver is the right place for this.

Please let me explain:

The origin of the failing high-speed negotiation is not because
of the ZynqMP specific hardware (so this particular specific DWC3
implementation), but because of the externally connected 
Microchip USB3340 ULPI PHY.

Meaning: Any DWC3 implementation which is connected to this particular
external ULPI PHY will have this high-speed negotiation problem.

On the other hand: If you connect a different ULPI PHY to the ZynqMP
DWC3 implementation, then this will work without any extra measures.
The Xilinx evaluation boards use other ULPI PHYs (USB3320), which is
why this problem didn't pop up with the Xilinx evaluation boards.

It's luck, that the dwc3 controller has a bit which allows it
to work together with this particular USB3340 ULPI PHY.

The property in the device tree describes the circuit implemented
on your hardware board:
If you have an externally USB3340 ULPI PHY connected to a 
DWC3 controller, then you have to set this new property.
If you have a different High-Speed USB PHY then you might not need
to set this property.
Of course this property will also help if you have a different
High-Speed PHY which has the same behavior as the USB3340 ULPI PHY
and so also requires setting the XCVRDLY bit.

I think any DWC3 implementation which allows to connect an external
ULPI PHY is affected by this problem.

So should I really move this property to the Xilinx specific glue driver?

with best regards
  Ingo

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Ingo ROHLOFF
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