From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx.nabladev.com (mx.nabladev.com [178.251.229.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A898F46A603; Fri, 28 Aug 2026 15:09:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.251.229.89 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787929795; cv=none; b=TlNLzxzeEMkk17Gg+GE0KfnYg5DFsFnOjBr48OYnmy8bYxpUYCEn6kgw2imqzb6/7z/HNt9RBtiEbl03QZLEOAxTlULTWFQYT3pbSgVXd8DaaciLI8V/JTf1pQa776uQHYskwka5XraEUmbiCkYlyJlBLJEko9qW9WQy2PG1KmY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787929795; c=relaxed/simple; bh=2ht7LSF54lpV7TrPbfz5U6zYSpkXQBDP5kxwisLOc6Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P6+M7O3xVs61sN82MR3cbRTqWKEP9aTvCQfzstIY82JrCWk9Am8R+PPmbTgGV60M3DEmkMNYYO5VgGkwDvzt+ZsXwml15gqe9J5+5VfmJAv31mMYxnVCq1AG1k0wBfV9YvdD6IB7jt8sRJLkC49pF5kS3urB9C0DOIQWwjyPUmY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com; spf=pass smtp.mailfrom=nabladev.com; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b=Jya9Q8Xk; arc=none smtp.client-ip=178.251.229.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nabladev.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nabladev.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nabladev.com header.i=@nabladev.com header.b="Jya9Q8Xk" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2C08E11D128; Fri, 28 Aug 2026 17:09:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com; s=dkim; t=1787929787; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=w4V2xYYZPxGiTt4YXxNmtjNTOnhx0km+lR8iVd4Fx10=; b=Jya9Q8XknBXVZsKtuL1AFEBOuKGqRuCmY2cdxrvpzdJ6zt6Y6+4lhqK0D0zc0wjMuVXOar GOZaRAy+3HQQzUShMt5YZ/ZOeCgb/pWg5v85uReUAFLNsaGiZ9vSQq4a/jTWJ0PR4jcYP0 oVpP7leKUAOnYOG4Y2uudcypVi110HZXHfjl9A9VgdUJuYRQbqOOx7R5vNpjGpbDBEOx+Z WzbHqtkTP6h/1B/o6NawYeg07XgcK3HsIAXv2mea7GPmfamUF2SSa79EEM8Zqf/E/m2U4s 1i7lWPAw2endyjWicvDMlerFGnHV2zowpgynmzmVbqlzYmIj/wE96z0sDdHbqA== From: Marek Vasut To: linux-usb@vger.kernel.org Cc: fabrice.gasnier@foss.st.com, Marek Vasut , Alexandre Torgue , Conor Dooley , Greg Kroah-Hartman , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , Thinh Nguyen , devicetree@vger.kernel.org, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v4 2/2] usb: dwc3: dwc3-generic-plat: Add ST STM32MP2 DWC3 xHCI USB controller glue Date: Fri, 28 Aug 2026 17:09:15 +0200 Message-ID: <20260828150937.174735-2-marex@nabladev.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260828150937.174735-1-marex@nabladev.com> References: <20260828150937.174735-1-marex@nabladev.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 The ST STM32MP2 SoC contains one instance of DWC3 USB controller with glue logic wrapper around it controlled by syscon. Extend the generic DWC3 platform driver with ST STM32MP2 glue logic specifics. Signed-off-by: Marek Vasut --- Cc: Alexandre Torgue Cc: Conor Dooley Cc: Fabrice Gasnier Cc: Greg Kroah-Hartman Cc: Krzysztof Kozlowski Cc: Marek Vasut Cc: Maxime Coquelin Cc: Rob Herring Cc: Thinh Nguyen Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-usb@vger.kernel.org --- V2: No change V3: - Use generic over-current-active-low V4: - Include bitfield.h - Split this from series arm64: dts: phy: st: usb: Add STM32MP2 USB support https://lore.kernel.org/all/20260822074816.548662-1-marex@nabladev.com/ --- drivers/usb/dwc3/dwc3-generic-plat.c | 45 ++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c index ca69ac0eb07ce..bb2be75a82875 100644 --- a/drivers/usb/dwc3/dwc3-generic-plat.c +++ b/drivers/usb/dwc3/dwc3-generic-plat.c @@ -7,6 +7,7 @@ * Inspired by dwc3-qcom.c and dwc3-of-simple.c */ +#include #include #include #include @@ -22,6 +23,12 @@ #define EIC7700_HSP_AXI_LP_XM_CSYSREQ BIT(0) #define EIC7700_HSP_AXI_LP_XS_CSYSREQ BIT(16) +#define STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT BIT(0) +#define STM32MP2_USB3DRCR_OVRCUR_POLARITY BIT(1) +#define STM32MP2_USB3DRCR_VBUSEN_POLARITY BIT(2) +#define STM32MP2_USB3DRCR_USB2ONLYH BIT(3) +#define STM32MP2_USB3DRCR_USB2ONLYD BIT(4) + struct dwc3_generic { struct device *dev; struct dwc3 dwc; @@ -85,6 +92,38 @@ static int dwc3_spacemit_k1_init(struct dwc3_generic *dwc3g) return 0; } +static int dwc3_stm32mp25_init(struct dwc3_generic *dwc3g) +{ + struct device *dev = dwc3g->dev; + bool ovrcur_polarity_low = device_property_read_bool(dev, "over-current-active-low"); + bool prt_pwr_ctrl = device_property_read_bool(dev, "st,enable-port-power-control"); + bool usb2only_conf = device_property_match_string(dev, "phy-names", "usb3-phy") < 0; + bool vbusen_polarity_low = device_property_read_bool(dev, "st,vbusen-active-low"); + struct regmap *regmap; + u32 drcr; + + regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, "st,syscfg", 1, &drcr); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "No st,syscfg phandle specified\n"); + + return regmap_update_bits(regmap, drcr, + STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT | + STM32MP2_USB3DRCR_OVRCUR_POLARITY | + STM32MP2_USB3DRCR_VBUSEN_POLARITY | + STM32MP2_USB3DRCR_USB2ONLYD | + STM32MP2_USB3DRCR_USB2ONLYH, + FIELD_PREP(STM32MP2_USB3DRCR_HOST_PORT_POWER_CONTROL_PRESENT, + prt_pwr_ctrl) | + FIELD_PREP(STM32MP2_USB3DRCR_OVRCUR_POLARITY, + ovrcur_polarity_low) | + FIELD_PREP(STM32MP2_USB3DRCR_VBUSEN_POLARITY, + vbusen_polarity_low) | + FIELD_PREP(STM32MP2_USB3DRCR_USB2ONLYD, + !!usb2only_conf) | + FIELD_PREP(STM32MP2_USB3DRCR_USB2ONLYH, + !!usb2only_conf)); +} + static int dwc3_generic_probe(struct platform_device *pdev) { const struct dwc3_generic_config *plat_config; @@ -231,12 +270,18 @@ static const struct dwc3_generic_config eic7700_dwc3 = { .properties = DWC3_DEFAULT_PROPERTIES, }; +static const struct dwc3_generic_config stm32mp25_dwc3 = { + .init = dwc3_stm32mp25_init, + .properties = DWC3_DEFAULT_PROPERTIES, +}; + static const struct of_device_id dwc3_generic_of_match[] = { { .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3}, { .compatible = "spacemit,k3-dwc3", }, { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3}, { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3}, { .compatible = "starfive,jhb100-dwc3", }, + { .compatible = "st,stm32mp25-dwc3", &stm32mp25_dwc3 }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, dwc3_generic_of_match); -- 2.53.0