From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CBA23DB63D; Sun, 6 Sep 2026 04:47:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788670021; cv=none; b=hSS+IQGJAsYsY4hgisC95Vesajkblci2rf+pNH1M+I+fIApUyCUh4ZJCWyuw86sbxRm2I1uHhqcx8ZU9ADO3FOcrQ/zF/dyF4jePyV8vdaQamw1JQdMEIY5Oz8a964aufb6QaH9tuImlUcualcxCkh2jOcihW7bvkmTvYkDJiFM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788670021; c=relaxed/simple; bh=Ikpi+gT4ywjhff6FSiJKyaOR6iEOydvAYf67drdysoM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lqzwvLymH+i7wse0UVVqXhj717hXxYuaoZSLx8sQDIRRIJZEIVqr6pxoowqfVWqWJQrJyXTHbON7XfdQ5ruqJwGL6zjs47AgtRK/32/mlLhpmO6WXbz+exEslP9EdNwPZyrLokqu+7sGBs4DBUgFuq/zoxlVI05giyMcRk4wSCY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=py9fKql1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="py9fKql1" Received: by smtp.kernel.org (Postfix) with ESMTPS id E9874C2BCFA; Sun, 6 Sep 2026 04:47:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1788670021; bh=Ikpi+gT4ywjhff6FSiJKyaOR6iEOydvAYf67drdysoM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=py9fKql15RS7DERbqSTcts9NS0y34IrwCqUZVZLIWLF5SWFSzsJeN/2iCmMmxdRVH 4GblO76Pq8VJpnrIKcxl6V/d8UuzjuFnfV826RKtKtYROusT2pBZeTXLUUwD5HKTcK zkqxvPbhDhW6uNUYs0m/PU5KTlbVP/GcmK0QDT/qNls+fQ1A+vZcT9epfX0l2Z4w1/ w9WHd55s+GxERCNbO/0yGQB/dWLDOJGudT9gcIUrV+kiNHRXW4D0zEEhku/Wj1IPXZ 5JEajI3ZvE7WV9ODzEtxqxFO/oclOJ0xsf9ZUfOqN5j6+n/pm5W+t5rZ89OMVVda3h khLbbuHcLap7g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C917CC79FA0; Sun, 6 Sep 2026 04:47:00 +0000 (UTC) From: George Moussalem via B4 Relay Date: Sun, 06 Sep 2026 08:46:41 +0400 Subject: [PATCH v3 02/10] usb: dwc3: qcom: Add support for selecting UTMI as reference clock Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260906-ipq-flatten-usb-v3-2-13e4e0f63123@outlook.com> References: <20260906-ipq-flatten-usb-v3-0-13e4e0f63123@outlook.com> In-Reply-To: <20260906-ipq-flatten-usb-v3-0-13e4e0f63123@outlook.com> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Thinh Nguyen , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan , George Moussalem X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1788670018; l=1928; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=o+kaADaB/p5iiIE1oFwC/8s5jkCmJhEr9uLhza+Gk4A=; b=jdoxNq02LkiVU+QjL52dFm4hoFrIyClozniAK3hpKN92xpLxs2NgMSqqRhfHI1+E5H+C8j/KZ TKvs9C59Ds1D2RK6MEsDvJRMBNGLmaS1BbILAb/4fa8lUksoqVSD6Ac X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem On many Qualcomm chipsets, the UTMI clock is used as the reference clock (ex. IPQ5018, IPQ6018, and IPQ9574 and more). Since moving to the new flattened snps-dwc3 model, it is no longer possible to pass the reference clock to the dwc3 core driver. The clock rate is used by the dwc3 core to compute the reference clock period and frame length adjustment. This is needed when the reference clock rate used computes values that deviate from the hardware defaults. Above mentioned SoCs require values different from the defaults and, as such, the core initializes with the wrong values which leads to non-functional USB operation. In Qualcomm chipsets, if available, the UTMI clock is used as the reference clock. Therefore, acquire the reference clock by name ('mock_utmi') and pass its clock rate to the core using the probe_data structure. Signed-off-by: George Moussalem --- drivers/usb/dwc3/dwc3-qcom.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index ac68b4218b56..8c1aca40c810 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -617,6 +617,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev) int ret; bool ignore_pipe_clk; bool wakeup_source; + struct clk *ref_clk; qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); if (!qcom) @@ -698,6 +699,14 @@ static int dwc3_qcom_probe(struct platform_device *pdev) qcom->current_role = USB_ROLE_DEVICE; } + ref_clk = devm_clk_get_optional(dev, "mock_utmi"); + if (IS_ERR(ref_clk)) { + ret = dev_err_probe(dev, PTR_ERR(ref_clk), "failed to get ref clock\n"); + goto clk_disable; + } else if (ref_clk) { + probe_data.ref_clk_rate = clk_get_rate(ref_clk); + } + qcom->dwc.glue_ops = &dwc3_qcom_glue_ops; qcom->dwc.dev = dev; -- 2.53.0