Re: [PATCH v5 1/4] dt-bindings: usb: add Altera Agilex5 DWC3 controller

[Conor Dooley <conor@kernel.org>]

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On Mon, Sep 07, 2026 at 04:21:38PM +0800, Adrian Ng Ho Yin wrote:
> Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3
> USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets,
> PHYs, and optional IOMMU support.
> 
> Clock names follow the snps,dwc3.yaml example order (bus_early, ref,
> suspend). Reset names use core/ecc. On this SoC ref and suspend are the
> same hardware source, so the example reuses AGILEX5_USB31_SUSPEND_CLK.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> ---
>  .../bindings/usb/altr,agilex5-dwc3.yaml       | 108 ++++++++++++++++++
>  1 file changed, 108 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> new file mode 100644
> index 000000000000..9970d7c9d6fa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera Agilex5 DWC3 USB SoC Controller
> +
> +maintainers:
> +  - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> +
> +description:
> +  The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3)
> +  controller that supports host, device and DRD modes.
> +
> +allOf:
> +  - $ref: snps,dwc3-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: altr,agilex5-dwc3
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Master/Core bus clock
> +      - description: Controller reference clock
> +      - description: Controller suspend clock
> +
> +  clock-names:
> +    items:
> +      - const: bus_early
> +      - const: ref
> +      - const: suspend
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  phys:
> +    minItems: 2
> +    maxItems: 2
> +
> +  phy-names:
> +    items:
> +      - const: usb2-phy
> +      - const: usb3-phy
> +
> +  iommus:
> +    maxItems: 1
> +
> +  resets:
> +    items:
> +      - description: DWC3 core reset
> +      - description: DWC3 ECC reset
> +
> +  reset-names:
> +    items:
> +      - const: core
> +      - const: ecc
> +
> +  dr_mode: true
> +
> +  maximum-speed: true
> +
> +  snps,dis_u2_susphy_quirk: true
> +
> +  snps,dis_u3_susphy_quirk: true

You add these two as possible but not required properties. Why is that?
Does the agilex5 have some instances of the IP where these are needed
and not others?


Cheers,
Conor.

> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - phys
> +  - phy-names
> +  - resets
> +  - reset-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/reset/altr,rst-mgr-s10.h>
> +    #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
> +
> +    soc {
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +
> +        usb@11000000 {
> +            compatible = "altr,agilex5-dwc3";
> +            reg = <0x11000000 0x100000>;
> +            interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +            clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>,
> +                     <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
> +                     <&clkmgr AGILEX5_USB31_SUSPEND_CLK>;
> +            clock-names = "bus_early", "ref", "suspend";
> +            phys = <&usbphy0>, <&usbphy1>;
> +            phy-names = "usb2-phy", "usb3-phy";
> +            resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
> +            reset-names = "core", "ecc";
> +            iommus = <&smmu 7>;
> +        };
> +    };
> -- 
> 2.49.GIT
> 

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