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Date: Fri, 11 Sep 2026 09:21:59 +0200
From: Krzysztof Kozlowski <krzk@kernel.org>
To: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, 
	Thinh Nguyen <Thinh.Nguyen@synopsys.com>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Dinh Nguyen <dinguyen@kernel.org>, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 2/4] arm64: dts: intel: agilex5: add USB3.1 controller
 node
Message-ID: <20260911-courageous-ninja-gibbon-9f8b0d@quoll>
References: <cover.1788886615.git.adrian.ho.yin.ng@altera.com>
 <17405f3736bb2fb20456d00b7bb75ffa8c1311b9.1788886615.git.adrian.ho.yin.ng@altera.com>
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In-Reply-To: <17405f3736bb2fb20456d00b7bb75ffa8c1311b9.1788886615.git.adrian.ho.yin.ng@altera.com>

On Wed, Sep 09, 2026 at 01:04:38AM +0800, Adrian Ng Ho Yin wrote:
> Add a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC.
> Place it under a simple-bus with a 40-bit dma-ranges window (#address-cells
> = 2) to match the USB DMA address width of the interconnect. Enable it in
> host mode on the SoCDK board.
> 
> ref and suspend both use AGILEX5_USB31_SUSPEND_CLK because they share the
> same hardware clock source on this SoC.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

Same comments apply. From 5 revisions ago!

Best regards,
Krzysztof