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Mon, 21 Sep 2026 05:19:34 -0700 From: Jon Hunter Date: Mon, 21 Sep 2026 13:19:07 +0100 Subject: [PATCH 7/9] usb: gadget: tegra-xudc: Add SSPX register offset to SoC data Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20260921-tegra-usb-v1-7-74a925a35d82@nvidia.com> References: <20260921-tegra-usb-v1-0-74a925a35d82@nvidia.com> In-Reply-To: <20260921-tegra-usb-v1-0-74a925a35d82@nvidia.com> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , "Nagarjuna Kristam" , JC Kuo , Mathias Nyman CC: Thierry Reding , , , , Thierry Reding , Wayne Chang , Jon Hunter X-Mailer: b4 0.16.1-dev X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|CH2PR12MB4104:EE_ X-MS-Office365-Filtering-Correlation-Id: ea5a643b-d7b4-487d-3b2a-08df17daa704 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|1800799024|376014|23010399003|10067099003|6133799003|22082099003|18002099003|11063799006|56012099006; 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In preparation for adding support for Tegra264, add the SSPX register offset into the SoC data and update the register definitions and register accesses to use the offset from the SoC data. Signed-off-by: Jon Hunter --- drivers/usb/gadget/udc/tegra-xudc.c | 90 ++++++++++++++++++++----------------- 1 file changed, 48 insertions(+), 42 deletions(-) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 0b88c1610f27..c97cacb7e416 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -143,42 +143,42 @@ #define HSFSPI_COUNT13_U2_RESUME_K_DURATION(x) ((x) & \ HSFSPI_COUNT13_U2_RESUME_K_DURATION_MASK) #define BLCG 0x840 -#define SSPX_CORE_CNT0 0x610 +#define SSPX_CORE_CNT0 0x10 #define SSPX_CORE_CNT0_PING_TBURST_MASK GENMASK(7, 0) #define SSPX_CORE_CNT0_PING_TBURST(x) ((x) & SSPX_CORE_CNT0_PING_TBURST_MASK) -#define SSPX_CORE_CNT30 0x688 +#define SSPX_CORE_CNT30 0x88 #define SSPX_CORE_CNT30_LMPITP_TIMER_MASK GENMASK(19, 0) #define SSPX_CORE_CNT30_LMPITP_TIMER(x) ((x) & \ SSPX_CORE_CNT30_LMPITP_TIMER_MASK) -#define SSPX_CORE_CNT32 0x690 +#define SSPX_CORE_CNT32 0x90 #define SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK GENMASK(7, 0) #define SSPX_CORE_CNT32_POLL_TBURST_MAX(x) ((x) & \ SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK) -#define SSPX_CORE_CNT56 0x6fc +#define SSPX_CORE_CNT56 0xfc #define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK GENMASK(19, 0) #define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(x) ((x) & \ SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK) -#define SSPX_CORE_CNT57 0x700 +#define SSPX_CORE_CNT57 0x100 #define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK GENMASK(19, 0) #define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(x) ((x) & \ SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK) -#define SSPX_CORE_CNT65 0x720 +#define SSPX_CORE_CNT65 0x120 #define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK GENMASK(19, 0) #define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(x) ((x) & \ SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK) -#define SSPX_CORE_CNT66 0x724 +#define SSPX_CORE_CNT66 0x124 #define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK GENMASK(19, 0) #define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(x) ((x) & \ SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK) -#define SSPX_CORE_CNT67 0x728 +#define SSPX_CORE_CNT67 0x128 #define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK GENMASK(19, 0) #define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(x) ((x) & \ SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK) -#define SSPX_CORE_CNT72 0x73c +#define SSPX_CORE_CNT72 0x13c #define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK GENMASK(19, 0) #define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(x) ((x) & \ SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK) -#define SSPX_CORE_PADCTL4 0x750 +#define SSPX_CORE_PADCTL4 0x150 #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK GENMASK(19, 0) #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(x) ((x) & \ SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK) @@ -548,6 +548,7 @@ struct tegra_xudc_soc { const char * const *clock_names; unsigned int num_clks; unsigned int num_phys; + unsigned int sspx_offset; bool u1_enable; bool u2_enable; bool lpm_enable; @@ -629,35 +630,35 @@ static void tegra_xudc_limit_port_speed(struct tegra_xudc *xudc) u32 val; /* limit port speed to gen 1 */ - val = xudc_readl(xudc, SSPX_CORE_CNT56); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT56); val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK); val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x260); - xudc_writel(xudc, val, SSPX_CORE_CNT56); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT56); - val = xudc_readl(xudc, SSPX_CORE_CNT57); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT57); val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK); val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x6D6); - xudc_writel(xudc, val, SSPX_CORE_CNT57); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT57); - val = xudc_readl(xudc, SSPX_CORE_CNT65); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT65); val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK); val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0x4B0); - xudc_writel(xudc, val, SSPX_CORE_CNT65); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT65); - val = xudc_readl(xudc, SSPX_CORE_CNT66); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT66); val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK); val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x4B0); - xudc_writel(xudc, val, SSPX_CORE_CNT66); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT66); - val = xudc_readl(xudc, SSPX_CORE_CNT67); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT67); val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK); val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x4B0); - xudc_writel(xudc, val, SSPX_CORE_CNT67); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT67); - val = xudc_readl(xudc, SSPX_CORE_CNT72); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT72); val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK); val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x10); - xudc_writel(xudc, val, SSPX_CORE_CNT72); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT72); } static void tegra_xudc_restore_port_speed(struct tegra_xudc *xudc) @@ -665,35 +666,35 @@ static void tegra_xudc_restore_port_speed(struct tegra_xudc *xudc) u32 val; /* restore port speed to gen2 */ - val = xudc_readl(xudc, SSPX_CORE_CNT56); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT56); val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK); val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x438); - xudc_writel(xudc, val, SSPX_CORE_CNT56); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT56); - val = xudc_readl(xudc, SSPX_CORE_CNT57); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT57); val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK); val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x528); - xudc_writel(xudc, val, SSPX_CORE_CNT57); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT57); - val = xudc_readl(xudc, SSPX_CORE_CNT65); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT65); val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK); val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0xE10); - xudc_writel(xudc, val, SSPX_CORE_CNT66); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT66); - val = xudc_readl(xudc, SSPX_CORE_CNT66); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT66); val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK); val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x348); - xudc_writel(xudc, val, SSPX_CORE_CNT66); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT66); - val = xudc_readl(xudc, SSPX_CORE_CNT67); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT67); val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK); val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x5a0); - xudc_writel(xudc, val, SSPX_CORE_CNT67); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT67); - val = xudc_readl(xudc, SSPX_CORE_CNT72); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT72); val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK); val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x1c21); - xudc_writel(xudc, val, SSPX_CORE_CNT72); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT72); } static void tegra_xudc_device_mode_on(struct tegra_xudc *xudc) @@ -3409,22 +3410,22 @@ static void tegra_xudc_device_params_init(struct tegra_xudc *xudc) tegra_xudc_limit_port_speed(xudc); /* Set a reasonable U3 exit timer value. */ - val = xudc_readl(xudc, SSPX_CORE_PADCTL4); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_PADCTL4); val &= ~(SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK); val |= SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(0x5dc0); - xudc_writel(xudc, val, SSPX_CORE_PADCTL4); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_PADCTL4); /* Default ping LFPS tBurst is too large. */ - val = xudc_readl(xudc, SSPX_CORE_CNT0); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT0); val &= ~(SSPX_CORE_CNT0_PING_TBURST_MASK); val |= SSPX_CORE_CNT0_PING_TBURST(0xa); - xudc_writel(xudc, val, SSPX_CORE_CNT0); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT0); /* Default tPortConfiguration timeout is too small. */ - val = xudc_readl(xudc, SSPX_CORE_CNT30); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT30); val &= ~(SSPX_CORE_CNT30_LMPITP_TIMER_MASK); val |= SSPX_CORE_CNT30_LMPITP_TIMER(0x978); - xudc_writel(xudc, val, SSPX_CORE_CNT30); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT30); if (xudc->soc->lpm_enable) { /* Set L1 resume duration to 95 us. */ @@ -3438,10 +3439,10 @@ static void tegra_xudc_device_params_init(struct tegra_xudc *xudc) * Compliance suite appears to be violating polling LFPS tBurst max * of 1.4us. Send 1.45us instead. */ - val = xudc_readl(xudc, SSPX_CORE_CNT32); + val = xudc_readl(xudc, xudc->soc->sspx_offset + SSPX_CORE_CNT32); val &= ~(SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK); val |= SSPX_CORE_CNT32_POLL_TBURST_MAX(0xb0); - xudc_writel(xudc, val, SSPX_CORE_CNT32); + xudc_writel(xudc, val, xudc->soc->sspx_offset + SSPX_CORE_CNT32); /* Direct HS/FS port instance to RxDetect. */ val = xudc_readl(xudc, CFG_DEV_FE); @@ -3641,6 +3642,7 @@ static struct tegra_xudc_soc tegra210_xudc_soc_data = { .clock_names = tegra210_xudc_clock_names, .num_clks = ARRAY_SIZE(tegra210_xudc_clock_names), .num_phys = 4, + .sspx_offset = 0x600, .u1_enable = false, .u2_enable = true, .lpm_enable = false, @@ -3655,6 +3657,7 @@ static struct tegra_xudc_soc tegra186_xudc_soc_data = { .clock_names = tegra186_xudc_clock_names, .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), .num_phys = 4, + .sspx_offset = 0x600, .u1_enable = true, .u2_enable = true, .lpm_enable = false, @@ -3669,6 +3672,7 @@ static struct tegra_xudc_soc tegra194_xudc_soc_data = { .clock_names = tegra186_xudc_clock_names, .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), .num_phys = 4, + .sspx_offset = 0x600, .u1_enable = true, .u2_enable = true, .lpm_enable = true, @@ -3683,6 +3687,7 @@ static struct tegra_xudc_soc tegra234_xudc_soc_data = { .clock_names = tegra186_xudc_clock_names, .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), .num_phys = 4, + .sspx_offset = 0x600, .u1_enable = true, .u2_enable = true, .lpm_enable = true, @@ -3696,6 +3701,7 @@ static struct tegra_xudc_soc tegra238_xudc_soc_data = { .clock_names = tegra186_xudc_clock_names, .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), .num_phys = 3, + .sspx_offset = 0x600, .u1_enable = true, .u2_enable = true, .lpm_enable = true, -- 2.43.0