Re: [PATCH] thunderbolt: Disable CL states for the Anker Prime TB5 dock

[Mika Westerberg <mika.westerberg@linux.intel.com>]

Hi,

On Sat, Sep 26, 2026 at 07:02:01AM +0000, Kurt Lieber wrote:
> Hello, 
> 
> On Fri, Sep 25, 2026 at 05:01:36AM +0000, Mika Westerberg wrote:
> > I just tried on my side MTL/PTL + BR Hub and works fine with CL0s/CL1
> > enabled. Also checked release notes of the NVM and there are no mention
> > about issues with CLx with the one you are running.
> >
> > There is one more thing that we can check though, can you run:
> >
> >   # tbdump -r 1 -a 1 -vv -N 1 PORT_CS_18
> >
> > and provide the output?
> 
> Route 1 is not present on this boot. The dock enumerated behind host
> port 3, so it is route 3. The upstream adapter is still 1. Read with
> the dock authorized and thunderbolt.clx=0 (tbtools aa0b1be):
> 
>   # tbdump -r 3 -a 1 -vv -N 1 PORT_CS_18
>   0x00d2 0x00f03510 0b00000000 11110000 00110101 00010000 PORT_CS_18
>     [00:07]       0x10 Cable USB4 Version
>     [08:08]        0x1 Bonding Enabled (BE)
>     [09:09]        0x0 TBT3-Compatible Mode (TCM)
>     [10:10]        0x1 CLx Protocol Support (CPS)
>     [11:11]        0x0 RS-FEC Enabled (Gen 2) (RE2)
>     [12:12]        0x1 RS-FEC Enabled (Gen 3) (RE3)
>     [13:13]        0x1 Router Detected (RD)
>     [16:16]        0x0 Wake on Connect Status
>     [17:17]        0x0 Wake on Disconnect Status
>     [18:18]        0x0 Wake on USB4 Wake Status
>     [19:19]        0x0 Wake on Inter-Domain Status
>     [20:20]        0x1 Cable Gen 3 Support (CG3)
>     [21:21]        0x1 Cable Gen 4 Support (CG4)
>     [22:22]        0x1 Cable Asymmetric Support (CSA)
>     [23:23]        0x1 Cable CLx Support (CSC)
>     [24:24]        0x0 AsymmetricTransitionInProgress (TIP)
> 
> The host downstream port on the other side of that link:
> 
>   # tbdump -r 0 -a 3 -vv -N 1 PORT_CS_18
>   0x00ae 0x00003510 0b00000000 00000000 00110101 00010000 PORT_CS_18
>     [00:07]       0x10 Cable USB4 Version
>     [08:08]        0x1 Bonding Enabled (BE)
>     [09:09]        0x0 TBT3-Compatible Mode (TCM)
>     [10:10]        0x1 CLx Protocol Support (CPS)
>     [11:11]        0x0 RS-FEC Enabled (Gen 2) (RE2)
>     [12:12]        0x1 RS-FEC Enabled (Gen 3) (RE3)
>     [13:13]        0x1 Router Detected (RD)
>     [16:16]        0x0 Wake on Connect Status
>     [17:17]        0x0 Wake on Disconnect Status
>     [18:18]        0x0 Wake on USB4 Wake Status
>     [19:19]        0x0 Wake on Inter-Domain Status
>     [20:20]        0x0 Cable Gen 3 Support (CG3)
>     [21:21]        0x0 Cable Gen 4 Support (CG4)
>     [22:22]        0x0 Cable Asymmetric Support (CSA)
>     [23:23]        0x0 Cable CLx Support (CSC)

This is the smoking gun! Thanks for taking the dump from the other side as
well. CM guide actually says we cannot enable CL states if this bit is not
set. Can you try the below patch (without clx=0)?

diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h
index 35ba8abe9ece..677b059cf088 100644
--- a/drivers/thunderbolt/tb_regs.h
+++ b/drivers/thunderbolt/tb_regs.h
@@ -391,6 +391,7 @@ struct tb_regs_port_header {
 #define PORT_CS_18_WODS				BIT(17)
 #define PORT_CS_18_WOU4S			BIT(18)
 #define PORT_CS_18_CSA				BIT(22)
+#define PORT_CS_18_CSC				BIT(23)
 #define PORT_CS_18_TIP				BIT(24)
 #define PORT_CS_19				0x13
 #define PORT_CS_19_DPR				BIT(0)
diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c
index f02c9f646833..1ce001c37c23 100644
--- a/drivers/thunderbolt/usb4.c
+++ b/drivers/thunderbolt/usb4.c
@@ -1662,7 +1662,11 @@ bool usb4_port_clx_supported(struct tb_port *port)
 	if (ret)
 		return false;
 
-	return !!(val & PORT_CS_18_CPS);
+	/* Both CPS and CSC must be set for CLx support */
+	if ((val & (PORT_CS_18_CPS | PORT_CS_18_CSC)) ==
+		(PORT_CS_18_CPS | PORT_CS_18_CSC))
+		return true;
+	return false;
 }
 
 /**