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Mon, 02 Nov 2026 13:51:22 -0800 (PST) Received: from DESKTOP-NM9EKIA ([125.134.240.130]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36a42935b4asm54710712eec.16.2026.11.02.13.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2026 13:51:21 -0800 (PST) From: Joonhoe Kim <26rote@gmail.com> To: gregkh@linuxfoundation.org, Thinh.Nguyen@synopsys.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org Cc: abelvesa@kernel.org, wesley.cheng@oss.qualcomm.com, krishna.kurapati@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, neil.armstrong@linaro.org, val@packett.cool, balaji.kalkonda@oss.qualcomm.com, tvlad744@gmail.com, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/3] usb: dwc3: qcom: Keep USB 2.0 working in DisplayPort-only modes Date: Tue, 3 Nov 2026 06:51:17 +0900 Message-ID: <20261102215121.738-1-26rote@gmail.com> X-Mailer: git-send-email 2.55.0.windows.5 X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit With a USB-C monitor in DisplayPort pin assignment C or E, the QMP USB3-DP combo PHY gives all four lanes to DisplayPort and keeps its USB PCS powered down. The USB 2.0 pair still works, and such monitors often have a USB 2.0 hub behind them, but the dwc3 controller keeps depending on the USB3 PIPE clock: on Kaanapali the next xHCI reset in this state times out ("Host halt failed, -110") and USB is gone until the cable is replugged. Commit f546912bcac6 ("phy: qcom: qmp-combo: Move pipe_clk on/off to common") keeps the pipe clock branch enabled, which is not enough here. This series lets the controller be a Type-C mode switch next to the PHY and moves it to the UTMI clock, the way "qcom,select-utmi-as-pipe-clk" does statically, before the PHY switches to DP-only mode. On Kaanapali the PHY becomes a mode switch with Balaji Kalkonda's DisplayPort series [1]; patch 3 is the controller side for the same SoC. Other SoCs whose PHY is already a mode switch (e.g. SM8650, SM8750) may need the same property on their controller node (not tested). Related fixes sent separately: "phy: qcom: qmp-combo: Leave the USB PCS alone in DP-only mode" (suspend in DP-only mode) [2] and "usb: typec: mux: fsa4480: Keep the USB 2.0 switch on in DP-only modes" (boards with an FSA4480 on the USB 2.0 pair) [3]. Patch 2 conflicts with Vladyslav Tymoshchuk's "usb: dwc3: qcom: Defer VBUS override update during system suspend" [4] in struct dwc3_qcom and dwc3_qcom_set_role_notifier(). On top of [4], the dwc3_qcom_update_pipe_clk() call goes after its pm_suspended check, as it also writes QSCRATCH. Patches 1-2 are for the USB tree. Patch 3 must not be applied before patch 2: with "mode-switch" on the controller and no mux registered by dwc3-qcom, pmic_glink_altmode defers its probe indefinitely. Tested on a Lenovo Y700 Gen 5 (TB323FU, Kaanapali) with a USB-C monitor over 4-lane HBR3: the monitor's USB 2.0 hub works at boot, after replugs and across s2idle (tested on v7.3 with these patches, [2] and [3]). [1] https://lore.kernel.org/all/20261022-kaanapali_dp-v3-0-b5ae8e6083c3@oss.qualcomm.com/ [2] https://lore.kernel.org/all/20261023123512.1912-1-26rote@gmail.com/ [3] https://lore.kernel.org/all/20261022165143.1327-1-26rote@gmail.com/ [4] https://lore.kernel.org/all/20261018143126.3978-1-tvlad744@gmail.com/ Joonhoe Kim (3): dt-bindings: usb: qcom,snps-dwc3: Add mode-switch usb: dwc3: qcom: Use the UTMI clock as PIPE clock in DisplayPort-only modes arm64: dts: qcom: kaanapali: Mark the USB controller as a Type-C mode switch .../bindings/usb/qcom,snps-dwc3.yaml | 7 ++ arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1 + drivers/usb/dwc3/dwc3-qcom.c | 94 +++++++++++++++++-- 3 files changed, 94 insertions(+), 8 deletions(-) base-commit: 7649ba73f9e7e1e04d0b46213e39c79ae09dd55c -- 2.43.0