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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 9-R9aySjuTjMOwr5e7jNZvIKELYi5aPX X-Proofpoint-ORIG-GUID: 9-R9aySjuTjMOwr5e7jNZvIKELYi5aPX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE4MDA3MyBTYWx0ZWRfXxr78fi8oiA+o 7OFVXhQU4VkWO73vBEFBXEcCJQGTKm0eoIwJX/jBYS8YX+zSMyUjCb9JpuTW+PMlo5cAvGbeeiS 9MB6zQ9aSu8OidRI42ezQdaY7jGGoEfKXLAZbsa8kbdBD/2EdlrDHIuqI5DaRLppnaTKukrtlWI iwMIGhfqsi/PnJDU1TYqgQyLmUF9yMe9vAC2yF41iNMWMt1GUtViWM6VsKzwQXcmFvStJPT/s1X jpQkoz1JqIAZNBtlpzCcSkSsY8wxbC2ZCHqfZZhcuWXT1fB/LsqZCLDqQlkUCIxbQhgPN6u3yz+ 6xsdqXa2yTqriEdXoai0eQTRxGvksHTyggbWTxkBB2rb9PxjlR8dA6wIERLfwaN8G+bo7pd9ivB ScjwtNphcsJRdLDgs1Iy7ewdz/R3rKSIiV00F1mPc00jvJM5P0RmWjIawoGM2TUCu8XeaNr8wKp uOnehEQfx9Td2FREqVw== X-Authority-Analysis: v=2.4 cv=Ruf16imK c=1 sm=1 tr=0 ts=6a842f5b cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=QSrdRFCPdf6-eOukQi8A:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODE4MDA3MyBTYWx0ZWRfX28uLXYEr6i5w qNhk1+CnvU13svfCWSHwj4oGo3bG6PoUBFIQVnUYDYiFFlS4ep5Bm4g9jJV60KlWvgwvf/oaarl e6Y3/kIDGVv1ujTNIpq0/U7PSbSKxK8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-17_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 bulkscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608180073 On 8/10/26 5:42 PM, Dmitry Baryshkov wrote: > Some PHYs need a final programming step after the host controller is > up: the Qualcomm HSIC PHY latches the device connect at the moment > HSIC mode is engaged, so that write must happen with the root port > already running, or an already-connected HSIC device (the strobe/data > lines have no hotplug) is never seen. The generic PHY framework > provides phy_calibrate() for exactly this kind of post-init fixup and > dwc3 already calls it; the chipidea host does not, leaving no place > for such PHY work. > > Call phy_calibrate() once the HCD has been added, next to the existing > i.MX HSIC active-event hook which serves the same purpose. PHYs > without a calibrate op are unaffected. > > Assisted-by: Claude:claude-fable-5 > Signed-off-by: Dmitry Baryshkov > --- PHY APIs happily eat nullptrs fwiw Reviewed-by: Konrad Dybcio Konrad > drivers/usb/chipidea/host.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c > index ced6076a8248..62bb2999edb6 100644 > --- a/drivers/usb/chipidea/host.c > +++ b/drivers/usb/chipidea/host.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > > #include "../host/ehci.h" > > @@ -192,6 +193,9 @@ static int host_start(struct ci_hdrc *ci) > (ci->platdata->flags & CI_HDRC_IMX_IS_HSIC)) > ci->platdata->notify_event > (ci, CI_HDRC_IMX_HSIC_ACTIVE_EVENT); > + > + if (ci->phy) > + phy_calibrate(ci->phy); > } > > return ret; >