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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bcac4849dfcsm75613566b.58.2026.05.08.05.04.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 May 2026 05:04:25 -0700 (PDT) Message-ID: <670f9a9f-54b9-4109-986e-5071caf1dcaf@oss.qualcomm.com> Date: Fri, 8 May 2026 14:04:23 +0200 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] usb: dwc3: Notify XHCI core of tunneled status To: Thinh Nguyen , Jack Pham Cc: Konrad Dybcio , Greg Kroah-Hartman , Mathias Nyman , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "usb4-upstream@oss.qualcomm.com" , Raghavendra Thoorpu , Mika Westerberg References: <20260505-topic-dwc3_tunneling_state-v1-0-4aaa6c3c14cb@oss.qualcomm.com> <20260505-topic-dwc3_tunneling_state-v1-2-4aaa6c3c14cb@oss.qualcomm.com> <1163a026-03b2-4860-a422-eb276920b4aa@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDEyNSBTYWx0ZWRfXx9rZfPNiZRID 1BmhxbRn3hy4E/95gkKdtb2JZJ6Gqu/YFsfK+22AkDcXdAuJxejmtW21Vhb/O1kZTE9/43pVSre c/XV9Ae9c0XxOJJKkR4C/cvSLmJoiNwViitjDP7+pWuJhYyCoITYvtA8iQumV1zeMwS94JXLWtn ngevfY2R8ZeaOyEp5Wd8d/+Rxbk/9gN1w37+1hqrGBH6VkqQNftF9W2Kd+V6Y/mu4Rcm31qaEFD Cj22NA/oW3FhdeNbOlC0VEnUL0l5sJfmKHDNlGZL/2JO1m3QHmVUgU3YodYxoQcUKZTWAKe2hZV pYUSAfA4LLVwKlS7AB68gL/JY7t+fEZ2glcTmkWYXs8bXP6VkDWIjQeP205AVPl2cXqFLelAgyn ZsJAForeowUszFRTM0C7YfMPv13Wi38KwYZkN3mvCQ26CEYEa2NfC+obEPfRKE3Oc0MkXLz+y5N A/LibRUQX0PZ0/KjAGA== X-Proofpoint-ORIG-GUID: cf0O8kID4LVs1Mm5gIpqmjAgVZOunR3u X-Proofpoint-GUID: cf0O8kID4LVs1Mm5gIpqmjAgVZOunR3u X-Authority-Analysis: v=2.4 cv=McxcfZ/f c=1 sm=1 tr=0 ts=69fdd14c cx=c_pps a=JIY1xp/sjQ9K5JH4t62bdg==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=2Dhs2t0eLDWaZkzIpxgA:9 a=QEXdDO2ut3YA:10 a=tNoRWFLymzeba-QzToBc:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080125 On 5/8/26 12:46 AM, Thinh Nguyen wrote: > On Thu, May 07, 2026, Jack Pham wrote: >> On Thu, May 07, 2026 at 12:34:50PM +0200, Konrad Dybcio wrote: >>> On 5/7/26 1:40 AM, Thinh Nguyen wrote: >>>> On Tue, May 05, 2026, Konrad Dybcio wrote: >>>>> From: Konrad Dybcio >>>>> >>>>> The Thunderbolt framework relies on the USB core to create device links >>>>> for tunneled ports, so that the USB3 controller is only kept >>>>> runtime-resumed for the duration of the tunneling. This depends on >>>>> first knowing whether a connection is tunneled or native. >>>>> >>>>> Add the logic to handle that for DWC3 controllers. >>>>> >>>>> Signed-off-by: Konrad Dybcio >>>>> --- >>>>> drivers/usb/dwc3/core.c | 12 ++++++++++++ >>>>> drivers/usb/dwc3/core.h | 18 ++++++++++++++++++ >>>>> drivers/usb/dwc3/host.c | 12 ++++++++++++ >>>>> 3 files changed, 42 insertions(+) >>>>> >>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c >>>>> index 65213896de99..7cec4911e278 100644 >>>>> --- a/drivers/usb/dwc3/core.c >>>>> +++ b/drivers/usb/dwc3/core.c >>>>> @@ -162,6 +162,18 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) >>>>> } >>>>> EXPORT_SYMBOL_GPL(dwc3_set_prtcap); >>>>> >>>>> +enum usb_link_tunnel_mode dwc3_link_tunnel_mode(struct dwc3 *dwc, u8 port) >>>>> +{ >>>>> + /* Prior versions had no CIO support */ >>>>> + if (!DWC3_VER_IS_WITHIN(DWC31, 191A, ANY)) >>>>> + return USB_LINK_NATIVE; >>>>> + >>>>> + if (dwc3_readl(dwc, DWC3_CIOCTRL(port)) & DWC3_CIOCTRL_CIO_EN) >>>> >>>> The CIO register block only exists if DWC1_USB31_EN_CIO is set (and >>>> DWC_USB31_EN_USB2_ONLY is not set). In most cases, this register block >>>> will be reserved, register read of reserved block should be 0. But we >>>> can't guarantee that it will always be the case. >>> >>> That's inconvenient because.. >>> >>> [...] >>> >>>> We shouldn't need to be doing this. This should be checked from the >>>> xHCI driver. Check xHCI spec for PORTSC.TM and USB3 tunneling support >>>> capability (section 7.11). >>> >>> ..I'm seeing only caps 0/1/2 (and 10 on some but not all) advertised >>> (I ran a for-loop checking offsets 0..=255) >> >> Right. That section in xHCI spec was only added in the 1.2b revision. >> However the DWC31 IP versions that current Qualcomm USB4-capable SoCs >> are using are 2.00a (and a customized version of 1.91a) which are only >> compliant to xHCI 1.1 so this capability is not there, even though the >> CIO register block exists. So short of having the proper XHCI bit, this >> is the next best, non-SoC specific alternative we've found that can >> allow XHCI driver to identify when it is operating in tunnel mode. >> > > I see. If you're using 2.00a, then we can't use the xHCI's capability > register and PORTSC.TM. > > Can we match the compatible string to check for CIO capability and have > this passed from your glue driver before accessing the CIO registers? Hm, we currently use a shared compatible string for the USB3+4 (1.91a-xxx) and USB2 (3.30a) hosts on the USB4-capable platforms.. Another idea would be to bail out if !device_property_present(dev, "usb4-host-interface") which would place the burden of making sure the DT makes sense on the programmer (which is OK in my view) Konrad