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([85.119.46.8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac2397363b7sm736352266b.121.2025.03.10.03.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 03:33:43 -0700 (PDT) Message-ID: <67cec007.170a0220.37245a.99cd@mx.google.com> X-Google-Original-Message-ID: Date: Mon, 10 Mar 2025 11:33:41 +0100 From: Christian Marangi To: Krzysztof Kozlowski Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger , AngeloGioacchino Del Regno , Greg Kroah-Hartman , Lorenzo Bianconi , Daniel Danzberger , Arnd Bergmann , Linus Walleij , Nikita Shubin , Guo Ren , Yangyu Chen , Ben Hutchings , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-usb@vger.kernel.org, upstream@airoha.com Subject: Re: [PATCH 04/13] dt-bindings: soc: airoha: add Documentation for Airoha AN7581 SCU SSR References: <20250309132959.19045-1-ansuelsmth@gmail.com> <20250309132959.19045-5-ansuelsmth@gmail.com> <20250310-aromatic-chihuahua-of-priority-4ee73b@krzk-bin> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250310-aromatic-chihuahua-of-priority-4ee73b@krzk-bin> On Mon, Mar 10, 2025 at 09:00:40AM +0100, Krzysztof Kozlowski wrote: > On Sun, Mar 09, 2025 at 02:29:35PM +0100, Christian Marangi wrote: > > The Airoha AN7581 SoC have in the SCU register space particular > > address that control how some peripheral are configured. > > > > These are toggeled in the System Status Register and are used to > > toggle Serdes port for USB 3.0 mode or HSGMII, USB 3.0 mode or PCIe2 > > or setup port for PCIe mode or Ethrnet mode (HSGMII/USXGMII). > > > > Modes are mutually exclusive and selecting one mode cause the > > other feature to not work (example a mode in USB 3.0 cause PCIe > > port 2 to not work) This depends also on what is physically > > connected to the Hardware and needs to correctly reflect the > > System Status Register bits. > > > > Special care is needed for PCIe port 0 in 2 line mode that > > requires both WiFi1 and WiFi2 Serdes port set to PCIe0 2 Line > > mode. > > > > Signed-off-by: Christian Marangi > > --- > > .../soc/airoha/airoha,an7581-scu-ssr.yaml | 106 ++++++++++++++++++ > > MAINTAINERS | 1 + > > 2 files changed, 107 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/soc/airoha/airoha,an7581-scu-ssr.yaml > > > > diff --git a/Documentation/devicetree/bindings/soc/airoha/airoha,an7581-scu-ssr.yaml b/Documentation/devicetree/bindings/soc/airoha/airoha,an7581-scu-ssr.yaml > > new file mode 100644 > > index 000000000000..4bbf6e3b79a4 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/airoha/airoha,an7581-scu-ssr.yaml > > @@ -0,0 +1,106 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/soc/airoha/airoha,an7581-scu-ssr.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Airoha AN7581 SCU System Status Register > > + > > +maintainers: > > + - Christian Marangi > > + > > +description: > > > + The Airoha AN7581 SoC have in the SCU register space particular > > + address that control how some peripheral are configured. > > + > > + These are toggeled in the System Status Register and are used to > > + toggle Serdes port for USB 3.0 mode or HSGMII, USB 3.0 mode or PCIe2 > > + or setup port for PCIe mode or Ethrnet mode (HSGMII/USXGMII). > > typo, Ethernet > > > + > > + Modes are mutually exclusive and selecting one mode cause the > > + other feature to not work (example a mode in USB 3.0 cause PCIe > > + port 2 to not work) This depends also on what is physically > > + connected to the Hardware and needs to correctly reflect the > > + System Status Register bits. > > + > > + Special care is needed for PCIe port 0 in 2 line mode that > > + requires both WiFi1 and WiFi2 Serdes port set to PCIe0 2 Line > > + mode. > > + > > +properties: > > + compatible: > > + const: airoha,an7581-scu-ssr > > That's not a separate device, but part of the SCU. > More comments on this in the MFD patch. > But more important - such definition of choice of serial engines is > really not flexible, not reabable and not helping integrating into DTS. > Are you going to grow this for next chip airoha,serdes-wifi20, then > airoha,serdes-wifi21, 22... ? And then how the if:then: would look like? > > Assuming you do not have here child-parent relationship, like usually > for serial engines, so then this should be somehow list of devices > (strings) you want to run. > You are right, string is more flexible and I don't need the include file. -- Ansuel