Re: [PATCH v3 3/4] dt-bindings: phy: google: Add Google Tensor G5 USB PHY

[Krzysztof Kozlowski <krzk@kernel.org>]

On 10/10/2025 22:16, Roy Luo wrote:
> +  reg:
> +    items:
> +      - description: USB2 PHY configuration registers.
> +      - description: DisplayPort top-level registers.
> +      - description: USB top-level configuration registers.
> +
> +  reg-names:
> +    items:
> +      - const: u2phy_cfg
> +      - const: dp_top
> +      - const: usb_top_cfg
> +
> +  "#phy-cells":
> +    const: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  orientation-switch:
> +    type: boolean
> +    description:
> +      Indicates the PHY as a handler of USB Type-C orientation changes
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - "#phy-cells"
> +  - clocks
> +  - resets
> +  - power-domains
> +  - orientation-switch
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        usb_phy: usb_phy@c410000 {
> +            compatible = "google,gs5-usb-phy";
> +            reg = <0 0x0c450014 0 0xc>,
> +                  <0 0x0c637000 0 0xa0>,

You probably miss DP support and this does not belong here.

> +                  <0 0x0c45002c 0 0x4>;

That's not a separate address space. I really, really doubt that
hardware engineers came with address spaces of one word long.

> +            reg-names = "u2phy_cfg", "dp_top", "usb_top_cfg";
> +            #phy-cells = <1>;
> +            clocks = <&hsion_usb2_phy_reset_clk>;
> +            resets = <&hsion_resets_usb2_phy>;
> +            power-domains = <&hsio_n_usb_pd>;
> +            orientation-switch;
> +        };
> +    };
> +...


Best regards,
Krzysztof