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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id u20sm150314wmj.14.2020.03.02.09.40.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Mar 2020 09:40:34 -0800 (PST) From: Kevin Hilman To: Kishon Vijay Abraham I Cc: Hanjie Lin , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, Carlo Caione , "Michael Turquette" , Stephen Boyd , "Martin Blumenstingl" , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Yue Wang , Xingyu Chen , Hanjie Lin , Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman Subject: Re: [PATCH v9 0/3] arm64: meson: Add support for USB on Amlogic A1 In-Reply-To: <1581990859-135234-1-git-send-email-hanjie.lin@amlogic.com> References: <1581990859-135234-1-git-send-email-hanjie.lin@amlogic.com> Date: Mon, 02 Mar 2020 18:40:34 +0100 Message-ID: <7hblper6y5.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Kishon, Hanjie Lin writes: > This patchset adds support for USB on Amlogic A1 SoCs. > > Because of my mistake I fogot to add PHY maintainer(Kishon) to mail list in > before versions, so I have to send this v8(and lateres) version again(only with dwc3 > bindings and driver patch removed). > > This patchset is composed with : > - bindings of the PHY > - bindings of the USB Control Glue(already accepted in v7) > - PHY Driver > - USB Control Glue driver(already accepted in v7) > - dts of the PHY and USB Controller > > The Amlogic A1 USB Complex is composed of : > - 1 DWC3 USB controller for USB2 Host functionality > - 1 USB2 PHY for USB2 Host functionality > > The USB Control Glue setups the clocks and the reset about DWC3 USB > controller, and binds to the USB2 PHY. It also configures the 8bit > UTMI interfaces for the USB2 PHY, including setting USB2 phy mode. > > The USB2 PHY driver initializes the phy analog settings, phy PLL > setup and phy tuning. > > This patchset is based on A1 clock/power domain/reset series at [0]. Gentle reminder ping. Once you pick up the bindings and driver (patches 1-2) I'll pick up the DT patch. Kevin