From: Felipe Balbi <balbi@kernel.org>
To: Thinh Nguyen <Thinh.Nguyen@synopsys.com>Thinh Nguyen
<Thinh.Nguyen@synopsys.com>,
linux-usb@vger.kernel.org
Cc: John Youn <John.Youn@synopsys.com>
Subject: [v4,01/15] usb: dwc3: Add SoftReset PHY synchonization delay
Date: Mon, 12 Mar 2018 12:23:53 +0200 [thread overview]
Message-ID: <87zi3d8udi.fsf@linux.intel.com> (raw)
Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
> From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
> bit is cleared, we must wait at least 50ms before accessing the PHY
> domain (synchronization delay).
>
> Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
checking file drivers/usb/dwc3/core.c
Hunk #1 FAILED at 228.
1 out of 1 hunk FAILED
next reply other threads:[~2018-03-12 10:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-12 10:23 Felipe Balbi [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-03-13 1:00 [v4,01/15] usb: dwc3: Add SoftReset PHY synchonization delay Thinh Nguyen
2018-01-31 21:14 Thinh Nguyen
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