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* [v4,01/15] usb: dwc3: Add SoftReset PHY synchonization delay
@ 2018-01-31 21:14 Thinh Nguyen
  0 siblings, 0 replies; 3+ messages in thread
From: Thinh Nguyen @ 2018-01-31 21:14 UTC (permalink / raw)
  To: Felipe Balbi, Thinh Nguyen, linux-usb; +Cc: John Youn

From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).

Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
---
 drivers/usb/dwc3/core.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 07832509584f..87043dd15b20 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -228,12 +228,23 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
 	do {
 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 		if (!(reg & DWC3_DCTL_CSFTRST))
-			return 0;
+			goto done;
 
 		udelay(1);
 	} while (--retries);
 
 	return -ETIMEDOUT;
+
+done:
+	/*
+	 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
+	 * we must wait at least 50ms before accessing the PHY domain
+	 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
+	 */
+	if (dwc3_is_usb31(dwc))
+		msleep(50);
+
+	return 0;
 }
 
 /*

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [v4,01/15] usb: dwc3: Add SoftReset PHY synchonization delay
@ 2018-03-12 10:23 Felipe Balbi
  0 siblings, 0 replies; 3+ messages in thread
From: Felipe Balbi @ 2018-03-12 10:23 UTC (permalink / raw)
  To: Thinh Nguyen; +Cc: John Youn

Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:

> From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
> bit is cleared, we must wait at least 50ms before accessing the PHY
> domain (synchronization delay).
>
> Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>

checking file drivers/usb/dwc3/core.c
Hunk #1 FAILED at 228.
1 out of 1 hunk FAILED

^ permalink raw reply	[flat|nested] 3+ messages in thread

* [v4,01/15] usb: dwc3: Add SoftReset PHY synchonization delay
@ 2018-03-13  1:00 Thinh Nguyen
  0 siblings, 0 replies; 3+ messages in thread
From: Thinh Nguyen @ 2018-03-13  1:00 UTC (permalink / raw)
  To: Felipe Balbi, Thinh Nguyen, linux-usb@vger.kernel.org; +Cc: John Youn

Hi Felipe,

On 3/12/2018 3:24 AM, Felipe Balbi wrote:
> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
> 
>>  From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
>> bit is cleared, we must wait at least 50ms before accessing the PHY
>> domain (synchronization delay).
>>
>> Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
> 
> checking file drivers/usb/dwc3/core.c
> Hunk #1 FAILED at 228.
> 1 out of 1 hunk FAILED
> 

I don't see conflict when applying this patch series to your next 
branch. The conflict is maybe from its previous version currently on 
your 'next' and 'testing/next' branch.

BR,
Thinh
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^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2018-03-13  1:00 UTC | newest]

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