* [PATCH v4 1/6] dt-bindings: interrupt-controller: Convert BCM7120 L2 to YAML
2021-12-17 4:19 [PATCH v4 0/6] Broadcom DT bindings updates to YAML Florian Fainelli
@ 2021-12-17 4:19 ` Florian Fainelli
2021-12-17 14:59 ` Rob Herring
2021-12-17 4:19 ` [PATCH v4 2/6] dt-bindings: interrupt-controller: Merge BCM3380 with BCM7120 Florian Fainelli
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Florian Fainelli @ 2021-12-17 4:19 UTC (permalink / raw)
To: devicetree
Cc: Florian Fainelli, Damien Le Moal, Rob Herring, Thomas Gleixner,
Marc Zyngier, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
Greg Kroah-Hartman, Al Cooper, Ray Jui, Scott Branden,
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:USB SUBSYSTEM
Convert the Broadcom BCM7120 Level 2 interrupt controller Device Tree
binding to YAML to help with validation.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../brcm,bcm7120-l2-intc.txt | 88 -------------
.../brcm,bcm7120-l2-intc.yaml | 124 ++++++++++++++++++
2 files changed, 124 insertions(+), 88 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
deleted file mode 100644
index addd86b6ca2f..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Broadcom BCM7120-style Level 2 interrupt controller
-
-This interrupt controller hardware is a second level interrupt controller that
-is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
-platforms. It can be found on BCM7xxx products starting with BCM7120.
-
-Such an interrupt controller has the following hardware design:
-
-- outputs multiple interrupts signals towards its interrupt controller parent
-
-- controls how some of the interrupts will be flowing, whether they will
- directly output an interrupt signal towards the interrupt controller parent,
- or if they will output an interrupt signal at this 2nd level interrupt
- controller, in particular for UARTs
-
-- has one 32-bit enable word and one 32-bit status word
-
-- no atomic set/clear operations
-
-- not all bits within the interrupt controller actually map to an interrupt
-
-The typical hardware layout for this controller is represented below:
-
-2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
-
-0 -----[ MUX ] ------------|==========> GIC interrupt 75
- \-----------\
- |
-1 -----[ MUX ] --------)---|==========> GIC interrupt 76
- \------------|
- |
-2 -----[ MUX ] --------)---|==========> GIC interrupt 77
- \------------|
- |
-3 ---------------------|
-4 ---------------------|
-5 ---------------------|
-7 ---------------------|---|===========> GIC interrupt 66
-9 ---------------------|
-10 --------------------|
-11 --------------------/
-
-6 ------------------------\
- |===========> GIC interrupt 64
-8 ------------------------/
-
-12 ........................ X
-13 ........................ X (not connected)
-..
-31 ........................ X
-
-Required properties:
-
-- compatible: should be "brcm,bcm7120-l2-intc"
-- reg: specifies the base physical address and size of the registers
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
- node, valid values depend on the type of parent interrupt controller
-- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
- are wired to this 2nd level interrupt controller, and how they match their
- respective interrupt parents. Should match exactly the number of interrupts
- specified in the 'interrupts' property.
-
-Optional properties:
-
-- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
- wakeup source for system suspend/resume.
-
-- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which
- have a mux gate, typically UARTs. Setting these bits will make their
- respective interrupt outputs bypass this 2nd level interrupt controller
- completely; it is completely transparent for the interrupt controller
- parent. This should have one 32-bit word per enable/status pair.
-
-Example:
-
-irq0_intc: interrupt-controller@f0406800 {
- compatible = "brcm,bcm7120-l2-intc";
- interrupt-parent = <&intc>;
- #interrupt-cells = <1>;
- reg = <0xf0406800 0x8>;
- interrupt-controller;
- interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
- brcm,int-map-mask = <0xeb8>, <0x140>;
- brcm,int-fwd-mask = <0x7>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
new file mode 100644
index 000000000000..e10c9879f3f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM7120-style Level 2 interrupt controller
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+description: >
+ This interrupt controller hardware is a second level interrupt controller that
+ is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
+ platforms. It can be found on BCM7xxx products starting with BCM7120.
+
+ Such an interrupt controller has the following hardware design:
+
+ - outputs multiple interrupts signals towards its interrupt controller parent
+
+ - controls how some of the interrupts will be flowing, whether they will
+ directly output an interrupt signal towards the interrupt controller parent,
+ or if they will output an interrupt signal at this 2nd level interrupt
+ controller, in particular for UARTs
+
+ - has one 32-bit enable word and one 32-bit status word
+
+ - no atomic set/clear operations
+
+ - not all bits within the interrupt controller actually map to an interrupt
+
+ The typical hardware layout for this controller is represented below:
+
+ 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
+
+ 0 -----[ MUX ] ------------|==========> GIC interrupt 75
+ \-----------\
+ |
+ 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
+ \------------|
+ |
+ 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
+ \------------|
+ |
+ 3 ---------------------|
+ 4 ---------------------|
+ 5 ---------------------|
+ 7 ---------------------|---|===========> GIC interrupt 66
+ 9 ---------------------|
+ 10 --------------------|
+ 11 --------------------/
+
+ 6 ------------------------\
+ |===========> GIC interrupt 64
+ 8 ------------------------/
+
+ 12 ........................ X
+ 13 ........................ X (not connected)
+ ..
+ 31 ........................ X
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ const: brcm,bcm7120-l2-intc
+
+ reg:
+ maxItems: 1
+ description: >
+ Specifies the base physical address and size of the registers
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupts: true
+
+ brcm,int-map-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: >
+ 32-bits bit mask describing how many and which interrupts are wired to
+ this 2nd level interrupt controller, and how they match their respective
+ interrupt parents. Should match exactly the number of interrupts
+ specified in the 'interrupts' property.
+
+ brcm,irq-can-wake:
+ type: boolean
+ description: >
+ If present, this means the L2 controller can be used as a wakeup source
+ for system suspend/resume.
+
+ brcm,int-fwd-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: >
+ if present, a bit mask to configure the interrupts which have a mux gate,
+ typically UARTs. Setting these bits will make their respective interrupt
+ outputs bypass this 2nd level interrupt controller completely; it is
+ completely transparent for the interrupt controller parent. This should
+ have one 32-bit word per enable/status pair.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+ - interrupts
+
+examples:
+ - |
+ irq0_intc: interrupt-controller@f0406800 {
+ compatible = "brcm,bcm7120-l2-intc";
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <1>;
+ reg = <0xf0406800 0x8>;
+ interrupt-controller;
+ interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+ brcm,int-map-mask = <0xeb8>, <0x140>;
+ brcm,int-fwd-mask = <0x7>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v4 1/6] dt-bindings: interrupt-controller: Convert BCM7120 L2 to YAML
2021-12-17 4:19 ` [PATCH v4 1/6] dt-bindings: interrupt-controller: Convert BCM7120 L2 " Florian Fainelli
@ 2021-12-17 14:59 ` Rob Herring
0 siblings, 0 replies; 12+ messages in thread
From: Rob Herring @ 2021-12-17 14:59 UTC (permalink / raw)
To: Florian Fainelli
Cc: devicetree, Damien Le Moal, Thomas Gleixner, Marc Zyngier,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Greg Kroah-Hartman,
Al Cooper, Ray Jui, Scott Branden,
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:USB SUBSYSTEM
On Thu, Dec 16, 2021 at 08:19:56PM -0800, Florian Fainelli wrote:
> Convert the Broadcom BCM7120 Level 2 interrupt controller Device Tree
> binding to YAML to help with validation.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../brcm,bcm7120-l2-intc.txt | 88 -------------
> .../brcm,bcm7120-l2-intc.yaml | 124 ++++++++++++++++++
> 2 files changed, 124 insertions(+), 88 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> deleted file mode 100644
> index addd86b6ca2f..000000000000
> --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
> +++ /dev/null
> @@ -1,88 +0,0 @@
> -Broadcom BCM7120-style Level 2 interrupt controller
> -
> -This interrupt controller hardware is a second level interrupt controller that
> -is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
> -platforms. It can be found on BCM7xxx products starting with BCM7120.
> -
> -Such an interrupt controller has the following hardware design:
> -
> -- outputs multiple interrupts signals towards its interrupt controller parent
> -
> -- controls how some of the interrupts will be flowing, whether they will
> - directly output an interrupt signal towards the interrupt controller parent,
> - or if they will output an interrupt signal at this 2nd level interrupt
> - controller, in particular for UARTs
> -
> -- has one 32-bit enable word and one 32-bit status word
> -
> -- no atomic set/clear operations
> -
> -- not all bits within the interrupt controller actually map to an interrupt
> -
> -The typical hardware layout for this controller is represented below:
> -
> -2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
> -
> -0 -----[ MUX ] ------------|==========> GIC interrupt 75
> - \-----------\
> - |
> -1 -----[ MUX ] --------)---|==========> GIC interrupt 76
> - \------------|
> - |
> -2 -----[ MUX ] --------)---|==========> GIC interrupt 77
> - \------------|
> - |
> -3 ---------------------|
> -4 ---------------------|
> -5 ---------------------|
> -7 ---------------------|---|===========> GIC interrupt 66
> -9 ---------------------|
> -10 --------------------|
> -11 --------------------/
> -
> -6 ------------------------\
> - |===========> GIC interrupt 64
> -8 ------------------------/
> -
> -12 ........................ X
> -13 ........................ X (not connected)
> -..
> -31 ........................ X
> -
> -Required properties:
> -
> -- compatible: should be "brcm,bcm7120-l2-intc"
> -- reg: specifies the base physical address and size of the registers
> -- interrupt-controller: identifies the node as an interrupt controller
> -- #interrupt-cells: specifies the number of cells needed to encode an interrupt
> - source, should be 1.
> -- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
> - node, valid values depend on the type of parent interrupt controller
> -- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
> - are wired to this 2nd level interrupt controller, and how they match their
> - respective interrupt parents. Should match exactly the number of interrupts
> - specified in the 'interrupts' property.
> -
> -Optional properties:
> -
> -- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
> - wakeup source for system suspend/resume.
> -
> -- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which
> - have a mux gate, typically UARTs. Setting these bits will make their
> - respective interrupt outputs bypass this 2nd level interrupt controller
> - completely; it is completely transparent for the interrupt controller
> - parent. This should have one 32-bit word per enable/status pair.
> -
> -Example:
> -
> -irq0_intc: interrupt-controller@f0406800 {
> - compatible = "brcm,bcm7120-l2-intc";
> - interrupt-parent = <&intc>;
> - #interrupt-cells = <1>;
> - reg = <0xf0406800 0x8>;
> - interrupt-controller;
> - interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
> - brcm,int-map-mask = <0xeb8>, <0x140>;
> - brcm,int-fwd-mask = <0x7>;
> -};
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
> new file mode 100644
> index 000000000000..e10c9879f3f8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
> @@ -0,0 +1,124 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Broadcom BCM7120-style Level 2 interrupt controller
> +
> +maintainers:
> + - Florian Fainelli <f.fainelli@gmail.com>
> +
> +description: >
> + This interrupt controller hardware is a second level interrupt controller that
> + is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
> + platforms. It can be found on BCM7xxx products starting with BCM7120.
> +
> + Such an interrupt controller has the following hardware design:
> +
> + - outputs multiple interrupts signals towards its interrupt controller parent
> +
> + - controls how some of the interrupts will be flowing, whether they will
> + directly output an interrupt signal towards the interrupt controller parent,
> + or if they will output an interrupt signal at this 2nd level interrupt
> + controller, in particular for UARTs
> +
> + - has one 32-bit enable word and one 32-bit status word
> +
> + - no atomic set/clear operations
> +
> + - not all bits within the interrupt controller actually map to an interrupt
> +
> + The typical hardware layout for this controller is represented below:
> +
> + 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
> +
> + 0 -----[ MUX ] ------------|==========> GIC interrupt 75
> + \-----------\
> + |
> + 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
> + \------------|
> + |
> + 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
> + \------------|
> + |
> + 3 ---------------------|
> + 4 ---------------------|
> + 5 ---------------------|
> + 7 ---------------------|---|===========> GIC interrupt 66
> + 9 ---------------------|
> + 10 --------------------|
> + 11 --------------------/
> +
> + 6 ------------------------\
> + |===========> GIC interrupt 64
> + 8 ------------------------/
> +
> + 12 ........................ X
> + 13 ........................ X (not connected)
> + ..
> + 31 ........................ X
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> + compatible:
> + const: brcm,bcm7120-l2-intc
> +
> + reg:
> + maxItems: 1
> + description: >
> + Specifies the base physical address and size of the registers
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 1
> +
> + interrupts: true
How many?
> +
> + brcm,int-map-mask:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: >
> + 32-bits bit mask describing how many and which interrupts are wired to
> + this 2nd level interrupt controller, and how they match their respective
> + interrupt parents. Should match exactly the number of interrupts
> + specified in the 'interrupts' property.
> +
> + brcm,irq-can-wake:
> + type: boolean
> + description: >
> + If present, this means the L2 controller can be used as a wakeup source
> + for system suspend/resume.
> +
> + brcm,int-fwd-mask:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: >
> + if present, a bit mask to configure the interrupts which have a mux gate,
> + typically UARTs. Setting these bits will make their respective interrupt
> + outputs bypass this 2nd level interrupt controller completely; it is
> + completely transparent for the interrupt controller parent. This should
> + have one 32-bit word per enable/status pair.
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupt-controller
> + - "#interrupt-cells"
> + - interrupts
> +
> +examples:
> + - |
> + irq0_intc: interrupt-controller@f0406800 {
> + compatible = "brcm,bcm7120-l2-intc";
> + interrupt-parent = <&intc>;
> + #interrupt-cells = <1>;
> + reg = <0xf0406800 0x8>;
> + interrupt-controller;
> + interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
> + brcm,int-map-mask = <0xeb8>, <0x140>;
> + brcm,int-fwd-mask = <0x7>;
> + };
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 2/6] dt-bindings: interrupt-controller: Merge BCM3380 with BCM7120
2021-12-17 4:19 [PATCH v4 0/6] Broadcom DT bindings updates to YAML Florian Fainelli
2021-12-17 4:19 ` [PATCH v4 1/6] dt-bindings: interrupt-controller: Convert BCM7120 L2 " Florian Fainelli
@ 2021-12-17 4:19 ` Florian Fainelli
2021-12-17 4:19 ` [PATCH v4 3/6] ARM: dts: NSP: Rename SATA unit name Florian Fainelli
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Florian Fainelli @ 2021-12-17 4:19 UTC (permalink / raw)
To: devicetree
Cc: Florian Fainelli, Damien Le Moal, Rob Herring, Thomas Gleixner,
Marc Zyngier, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
Greg Kroah-Hartman, Al Cooper, Ray Jui, Scott Branden,
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:USB SUBSYSTEM
The two bindings are very similar and should be covered by the same
document, do that so we can get rid of an additional binding file.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../brcm,bcm3380-l2-intc.txt | 39 -------------------
.../brcm,bcm7120-l2-intc.yaml | 31 +++++++++++++--
2 files changed, 28 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
deleted file mode 100644
index 37aea40d5430..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
-
-This interrupt controller shows up in various forms on many BCM338x/BCM63xx
-chipsets. It has the following properties:
-
-- outputs a single interrupt signal to its interrupt controller parent
-
-- contains one or more enable/status word pairs, which often appear at
- different offsets in different blocks
-
-- no atomic set/clear operations
-
-Required properties:
-
-- compatible: should be "brcm,bcm3380-l2-intc"
-- reg: specifies one or more enable/status pairs, in the following format:
- <enable_reg 0x4 status_reg 0x4>...
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- interrupts: specifies the interrupt line in the interrupt-parent controller
- node, valid values depend on the type of parent interrupt controller
-
-Optional properties:
-
-- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
- wakeup source for system suspend/resume.
-
-Example:
-
-irq0_intc: interrupt-controller@10000020 {
- compatible = "brcm,bcm3380-l2-intc";
- reg = <0x10000024 0x4 0x1000002c 0x4>,
- <0x10000020 0x4 0x10000028 0x4>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&cpu_intc>;
- interrupts = <2>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
index e10c9879f3f8..d24493fe246c 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Broadcom BCM7120-style Level 2 interrupt controller
+title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
@@ -59,15 +59,29 @@ description: >
..
31 ........................ X
+ The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
+ on many BCM338x/BCM63xx chipsets. It has the following properties:
+
+ - outputs a single interrupt signal to its interrupt controller parent
+
+ - contains one or more enable/status word pairs, which often appear at
+ different offsets in different blocks
+
+ - no atomic set/clear operations
+
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
- const: brcm,bcm7120-l2-intc
+ items:
+ - enum:
+ - brcm,bcm7120-l2-intc
+ - brcm,bcm3380-l2-intc
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
description: >
Specifies the base physical address and size of the registers
@@ -122,3 +136,14 @@ examples:
brcm,int-map-mask = <0xeb8>, <0x140>;
brcm,int-fwd-mask = <0x7>;
};
+
+ - |
+ irq1_intc: interrupt-controller@10000020 {
+ compatible = "brcm,bcm3380-l2-intc";
+ reg = <0x10000024 0x4>, <0x1000002c 0x4>,
+ <0x10000020 0x4>, <0x10000028 0x4>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <2>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v4 3/6] ARM: dts: NSP: Rename SATA unit name
2021-12-17 4:19 [PATCH v4 0/6] Broadcom DT bindings updates to YAML Florian Fainelli
2021-12-17 4:19 ` [PATCH v4 1/6] dt-bindings: interrupt-controller: Convert BCM7120 L2 " Florian Fainelli
2021-12-17 4:19 ` [PATCH v4 2/6] dt-bindings: interrupt-controller: Merge BCM3380 with BCM7120 Florian Fainelli
@ 2021-12-17 4:19 ` Florian Fainelli
2021-12-17 16:02 ` Florian Fainelli
2021-12-17 4:19 ` [PATCH v4 4/6] dt-bindings: ata: Convert Broadcom SATA to YAML Florian Fainelli
` (2 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Florian Fainelli @ 2021-12-17 4:19 UTC (permalink / raw)
To: devicetree
Cc: Florian Fainelli, Damien Le Moal, Rob Herring, Thomas Gleixner,
Marc Zyngier, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
Greg Kroah-Hartman, Al Cooper, Ray Jui, Scott Branden,
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:USB SUBSYSTEM
Rename the SATA controller unit name from ahci to sata in preparation
for adding the Broadcom SATA3 controller YAML binding which will bring
validation.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 1c08daa18858..ded5a59e0679 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -534,7 +534,7 @@ sata_phy1: sata-phy@1 {
};
};
- sata: ahci@41000 {
+ sata: sata@41000 {
compatible = "brcm,bcm-nsp-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0x41000 0x1000>, <0x40020 0x1c>;
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v4 3/6] ARM: dts: NSP: Rename SATA unit name
2021-12-17 4:19 ` [PATCH v4 3/6] ARM: dts: NSP: Rename SATA unit name Florian Fainelli
@ 2021-12-17 16:02 ` Florian Fainelli
0 siblings, 0 replies; 12+ messages in thread
From: Florian Fainelli @ 2021-12-17 16:02 UTC (permalink / raw)
To: Florian Fainelli, devicetree
Cc: Damien Le Moal, Rob Herring, Thomas Gleixner, Marc Zyngier,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Greg Kroah-Hartman,
Al Cooper, Ray Jui, Scott Branden,
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:USB SUBSYSTEM
On 12/16/2021 8:19 PM, Florian Fainelli wrote:
> Rename the SATA controller unit name from ahci to sata in preparation
> for adding the Broadcom SATA3 controller YAML binding which will bring
> validation.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Applied to devicetree/next!
--
Florian
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 4/6] dt-bindings: ata: Convert Broadcom SATA to YAML
2021-12-17 4:19 [PATCH v4 0/6] Broadcom DT bindings updates to YAML Florian Fainelli
` (2 preceding siblings ...)
2021-12-17 4:19 ` [PATCH v4 3/6] ARM: dts: NSP: Rename SATA unit name Florian Fainelli
@ 2021-12-17 4:19 ` Florian Fainelli
2021-12-17 15:00 ` Rob Herring
2021-12-17 4:20 ` [PATCH v4 5/6] dt-bindings: bus: Convert GISB arbiter " Florian Fainelli
2021-12-17 4:20 ` [PATCH v4 6/6] dt-bindings: usb: Convert BDC " Florian Fainelli
5 siblings, 1 reply; 12+ messages in thread
From: Florian Fainelli @ 2021-12-17 4:19 UTC (permalink / raw)
To: devicetree
Cc: Florian Fainelli, Damien Le Moal, Rob Herring, Thomas Gleixner,
Marc Zyngier, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
Greg Kroah-Hartman, Al Cooper, Ray Jui, Scott Branden,
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:USB SUBSYSTEM
Convert the Broadcom SATA3 AHCI controller Device Tree binding to YAML
to help with validation.
Acked-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../bindings/ata/brcm,sata-brcm.txt | 45 ----------
.../bindings/ata/brcm,sata-brcm.yaml | 90 +++++++++++++++++++
2 files changed, 90 insertions(+), 45 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
deleted file mode 100644
index b9ae4ce4a0a0..000000000000
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-* Broadcom SATA3 AHCI Controller
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-Each SATA controller should have its own node.
-
-Required properties:
-- compatible : should be one or more of
- "brcm,bcm7216-ahci"
- "brcm,bcm7425-ahci"
- "brcm,bcm7445-ahci"
- "brcm,bcm-nsp-ahci"
- "brcm,sata3-ahci"
- "brcm,bcm63138-ahci"
-- reg : register mappings for AHCI and SATA_TOP_CTRL
-- reg-names : "ahci" and "top-ctrl"
-- interrupts : interrupt mapping for SATA IRQ
-
-Optional properties:
-
-- reset: for "brcm,bcm7216-ahci" must be a valid reset phandle
- pointing to the RESCAL reset controller provider node.
-- reset-names: for "brcm,bcm7216-ahci", must be "rescal".
-
-Also see ahci-platform.txt.
-
-Example:
-
- sata@f045a000 {
- compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
- reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
- reg-names = "ahci", "top-ctrl";
- interrupts = <0 30 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- sata0: sata-port@0 {
- reg = <0>;
- phys = <&sata_phy 0>;
- };
-
- sata1: sata-port@1 {
- reg = <1>;
- phys = <&sata_phy 1>;
- };
- };
diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
new file mode 100644
index 000000000000..235a93ac86b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom SATA3 AHCI Controller
+
+description:
+ SATA nodes are defined to describe on-chip Serial ATA controllers.
+ Each SATA controller should have its own node.
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+allOf:
+ - $ref: sata-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,bcm7216-ahci
+ - brcm,bcm7445-ahci
+ - brcm,bcm7425-ahci
+ - brcm,bcm63138-ahci
+ - const: brcm,sata3-ahci
+ - items:
+ - const: brcm,bcm-nsp-ahci
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: ahci
+ - const: top-ctrl
+
+ interrupts:
+ maxItems: 1
+
+ dma-coherent: true
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,bcm7216-ahci
+ - brcm,bcm63138-ahci
+then:
+ properties:
+ resets:
+ maxItems: 1
+ reset-names:
+ enum:
+ - rescal
+ - ahci
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ sata@f045a000 {
+ compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
+ reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
+ reg-names = "ahci", "top-ctrl";
+ interrupts = <0 30 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy 0>;
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ phys = <&sata_phy 1>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v4 4/6] dt-bindings: ata: Convert Broadcom SATA to YAML
2021-12-17 4:19 ` [PATCH v4 4/6] dt-bindings: ata: Convert Broadcom SATA to YAML Florian Fainelli
@ 2021-12-17 15:00 ` Rob Herring
0 siblings, 0 replies; 12+ messages in thread
From: Rob Herring @ 2021-12-17 15:00 UTC (permalink / raw)
To: Florian Fainelli
Cc: Marc Zyngier, Al Cooper, linux-ide, linux-arm-kernel, Ray Jui,
devicetree, bcm-kernel-feedback-list, linux-kernel, linux-usb,
Damien Le Moal, Scott Branden, Thomas Gleixner, Rob Herring,
Greg Kroah-Hartman
On Thu, 16 Dec 2021 20:19:59 -0800, Florian Fainelli wrote:
> Convert the Broadcom SATA3 AHCI controller Device Tree binding to YAML
> to help with validation.
>
> Acked-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../bindings/ata/brcm,sata-brcm.txt | 45 ----------
> .../bindings/ata/brcm,sata-brcm.yaml | 90 +++++++++++++++++++
> 2 files changed, 90 insertions(+), 45 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
> create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 5/6] dt-bindings: bus: Convert GISB arbiter to YAML
2021-12-17 4:19 [PATCH v4 0/6] Broadcom DT bindings updates to YAML Florian Fainelli
` (3 preceding siblings ...)
2021-12-17 4:19 ` [PATCH v4 4/6] dt-bindings: ata: Convert Broadcom SATA to YAML Florian Fainelli
@ 2021-12-17 4:20 ` Florian Fainelli
2021-12-17 15:01 ` Rob Herring
2021-12-17 4:20 ` [PATCH v4 6/6] dt-bindings: usb: Convert BDC " Florian Fainelli
5 siblings, 1 reply; 12+ messages in thread
From: Florian Fainelli @ 2021-12-17 4:20 UTC (permalink / raw)
To: devicetree
Cc: Florian Fainelli, Damien Le Moal, Rob Herring, Thomas Gleixner,
Marc Zyngier, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
Greg Kroah-Hartman, Al Cooper, Ray Jui, Scott Branden,
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:USB SUBSYSTEM
Convert the Broadcom STB GISB bus arbiter to YAML to help with
validation.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/bus/brcm,gisb-arb.txt | 34 ----------
.../bindings/bus/brcm,gisb-arb.yaml | 66 +++++++++++++++++++
2 files changed, 66 insertions(+), 34 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
create mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
deleted file mode 100644
index 10f6d0a8159d..000000000000
--- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Broadcom GISB bus Arbiter controller
-
-Required properties:
-
-- compatible:
- "brcm,bcm7278-gisb-arb" for V7 28nm chips
- "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
- "brcm,bcm7435-gisb-arb" for newer 40nm chips
- "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
- "brcm,bcm7038-gisb-arb" for 130nm chips
-- reg: specifies the base physical address and size of the registers
-- interrupts: specifies the two interrupts (timeout and TEA) to be used from
- the parent interrupt controller. A third optional interrupt may be specified
- for breakpoints.
-
-Optional properties:
-
-- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
- masters are valid at the system level
-- brcm,gisb-arb-master-names: string list of the litteral name of the GISB
- masters. Should match the number of bits set in brcm,gisb-master-mask and
- the order in which they appear
-
-Example:
-
-gisb-arb@f0400000 {
- compatible = "brcm,gisb-arb";
- reg = <0xf0400000 0x800>;
- interrupts = <0>, <2>;
- interrupt-parent = <&sun_l2_intc>;
-
- brcm,gisb-arb-master-mask = <0x7>;
- brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
-};
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
new file mode 100644
index 000000000000..b23c3001991e
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom GISB bus Arbiter controller
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,bcm7445-gisb-arb # for other 28nm chips
+ - const: brcm,gisb-arb
+ - items:
+ - enum:
+ - brcm,bcm7278-gisb-arb # for V7 28nm chips
+ - brcm,bcm7435-gisb-arb # for newer 40nm chips
+ - brcm,bcm7400-gisb-arb # for older 40nm chips and all 65nm chips
+ - brcm,bcm7038-gisb-arb # for 130nm chips
+ - brcm,gisb-arb # fallback compatible
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ items:
+ - description: timeout interrupt line
+ - description: target abort interrupt line
+ - description: breakpoint interrupt line
+
+ brcm,gisb-arb-master-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: >
+ 32-bits wide bitmask used to specify which GISB masters are valid at the
+ system level
+
+ brcm,gisb-arb-master-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: >
+ String list of the litteral name of the GISB masters. Should match the
+ number of bits set in brcm,gisb-master-mask and the order in which they
+ appear from MSB to LSB.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ gisb-arb@f0400000 {
+ compatible = "brcm,gisb-arb";
+ reg = <0xf0400000 0x800>;
+ interrupts = <0>, <2>;
+ interrupt-parent = <&sun_l2_intc>;
+ brcm,gisb-arb-master-mask = <0x7>;
+ brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v4 5/6] dt-bindings: bus: Convert GISB arbiter to YAML
2021-12-17 4:20 ` [PATCH v4 5/6] dt-bindings: bus: Convert GISB arbiter " Florian Fainelli
@ 2021-12-17 15:01 ` Rob Herring
0 siblings, 0 replies; 12+ messages in thread
From: Rob Herring @ 2021-12-17 15:01 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-arm-kernel, linux-ide, Damien Le Moal, Rob Herring,
Thomas Gleixner, devicetree, linux-usb, Ray Jui, linux-kernel,
Marc Zyngier, Greg Kroah-Hartman, Al Cooper, Scott Branden,
bcm-kernel-feedback-list
On Thu, 16 Dec 2021 20:20:00 -0800, Florian Fainelli wrote:
> Convert the Broadcom STB GISB bus arbiter to YAML to help with
> validation.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../devicetree/bindings/bus/brcm,gisb-arb.txt | 34 ----------
> .../bindings/bus/brcm,gisb-arb.yaml | 66 +++++++++++++++++++
> 2 files changed, 66 insertions(+), 34 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
> create mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 6/6] dt-bindings: usb: Convert BDC to YAML
2021-12-17 4:19 [PATCH v4 0/6] Broadcom DT bindings updates to YAML Florian Fainelli
` (4 preceding siblings ...)
2021-12-17 4:20 ` [PATCH v4 5/6] dt-bindings: bus: Convert GISB arbiter " Florian Fainelli
@ 2021-12-17 4:20 ` Florian Fainelli
2021-12-17 15:04 ` Rob Herring
5 siblings, 1 reply; 12+ messages in thread
From: Florian Fainelli @ 2021-12-17 4:20 UTC (permalink / raw)
To: devicetree
Cc: Florian Fainelli, Damien Le Moal, Rob Herring, Thomas Gleixner,
Marc Zyngier, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
Greg Kroah-Hartman, Al Cooper, Ray Jui, Scott Branden,
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list, moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE,
open list:USB SUBSYSTEM
Convert the Broadcom BDC device controller Device Tree binding to YAML
to help with validation.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../devicetree/bindings/usb/brcm,bdc.txt | 29 -----------
.../devicetree/bindings/usb/brcm,bdc.yaml | 49 +++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 50 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.txt
create mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.yaml
diff --git a/Documentation/devicetree/bindings/usb/brcm,bdc.txt b/Documentation/devicetree/bindings/usb/brcm,bdc.txt
deleted file mode 100644
index c9f52b97cef1..000000000000
--- a/Documentation/devicetree/bindings/usb/brcm,bdc.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Broadcom USB Device Controller (BDC)
-====================================
-
-Required properties:
-
-- compatible: must be one of:
- "brcm,bdc-udc-v2"
- "brcm,bdc"
-- reg: the base register address and length
-- interrupts: the interrupt line for this controller
-
-Optional properties:
-
-On Broadcom STB platforms, these properties are required:
-
-- phys: phandle to one or two USB PHY blocks
- NOTE: Some SoC's have a single phy and some have
- USB 2.0 and USB 3.0 phys
-- clocks: phandle to the functional clock of this block
-
-Example:
-
- bdc@f0b02000 {
- compatible = "brcm,bdc-udc-v2";
- reg = <0xf0b02000 0xfc4>;
- interrupts = <0x0 0x60 0x0>;
- phys = <&usbphy_0 0x0>;
- clocks = <&sw_usbd>;
- };
diff --git a/Documentation/devicetree/bindings/usb/brcm,bdc.yaml b/Documentation/devicetree/bindings/usb/brcm,bdc.yaml
new file mode 100644
index 000000000000..f72dc65d4919
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/brcm,bdc.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/brcm,bdc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom USB Device Controller (BDC)
+
+maintainers:
+ - Al Cooper <alcooperx@gmail.com>
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - brcm,bdc-udc-v2
+ - brcm,bdc
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+
+ phys:
+ minItems: 1
+ items:
+ - description: USB 2.0 or 3.0 PHY
+ - description: USB 3.0 PHY if there is a dedicated 2.0 PHY
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ usb@f0b02000 {
+ compatible = "brcm,bdc-udc-v2";
+ reg = <0xf0b02000 0xfc4>;
+ interrupts = <0x0 0x60 0x0>;
+ phys = <&usbphy_0 0x0>;
+ clocks = <&sw_usbd>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index b5b7dcaba8b6..4a8356add1c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3679,7 +3679,7 @@ M: Al Cooper <alcooperx@gmail.com>
L: linux-usb@vger.kernel.org
L: bcm-kernel-feedback-list@broadcom.com
S: Maintained
-F: Documentation/devicetree/bindings/usb/brcm,bdc.txt
+F: Documentation/devicetree/bindings/usb/brcm,bdc.yaml
F: drivers/usb/gadget/udc/bdc/
BROADCOM BMIPS CPUFREQ DRIVER
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v4 6/6] dt-bindings: usb: Convert BDC to YAML
2021-12-17 4:20 ` [PATCH v4 6/6] dt-bindings: usb: Convert BDC " Florian Fainelli
@ 2021-12-17 15:04 ` Rob Herring
0 siblings, 0 replies; 12+ messages in thread
From: Rob Herring @ 2021-12-17 15:04 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-ide, Greg Kroah-Hartman, Damien Le Moal, linux-arm-kernel,
Al Cooper, devicetree, Thomas Gleixner, bcm-kernel-feedback-list,
Marc Zyngier, Scott Branden, linux-kernel, Rob Herring, linux-usb,
Ray Jui
On Thu, 16 Dec 2021 20:20:01 -0800, Florian Fainelli wrote:
> Convert the Broadcom BDC device controller Device Tree binding to YAML
> to help with validation.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../devicetree/bindings/usb/brcm,bdc.txt | 29 -----------
> .../devicetree/bindings/usb/brcm,bdc.yaml | 49 +++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 50 insertions(+), 30 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.txt
> create mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 12+ messages in thread