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[34.125.176.30]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad815835sm130651b3a.27.2024.12.18.17.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 17:32:42 -0800 (PST) Date: Thu, 19 Dec 2024 01:32:38 +0000 From: Benson Leung To: Abhishek Pandit-Subedi Cc: heikki.krogerus@linux.intel.com, tzungbi@kernel.org, linux-usb@vger.kernel.org, chrome-platform@lists.linux.dev, akuchynski@google.com, sboyd@kernel.org, pmalani@chromium.org, badhri@google.com, rdbabiera@google.com, dmitry.baryshkov@linaro.org, jthies@google.com, Benson Leung , Guenter Roeck , linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 8/8] platform/chrome: cros_ec_typec: Disable tbt on port Message-ID: References: <20241213233552.451927-1-abhishekpandit@chromium.org> <20241213153543.v5.8.Ic14738918e3d026fa2d85e95fb68f8e07a0828d0@changeid> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="W8cAO6hx+FSI0lHc" Content-Disposition: inline In-Reply-To: <20241213153543.v5.8.Ic14738918e3d026fa2d85e95fb68f8e07a0828d0@changeid> --W8cAO6hx+FSI0lHc Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Dec 13, 2024 at 03:35:49PM -0800, Abhishek Pandit-Subedi wrote: > Altmodes with cros_ec are either automatically entered by the EC or > entered by the AP if TBT or USB4 are supported on the system. Due to the > security risk of PCIe tunneling, TBT modes should not be auto entered by > the kernel at this time and will require user intervention. >=20 > With this change, a userspace program will need to explicitly activate > the thunderbolt mode on the port and partner in order to enter the mode > and the thunderbolt driver will not automatically enter when a partner > is connected. >=20 > Signed-off-by: Abhishek Pandit-Subedi Reviewed-by: Benson Leung > --- >=20 > (no changes since v3) >=20 > Changes in v3: > - Set port.inactive =3D true instead of auto-enter. >=20 > Changes in v2: > - Only disable auto-enter for Thunderbolt > - Update commit message to clearly indicate the need for userspace > intervention to enter TBT mode >=20 > drivers/platform/chrome/cros_ec_typec.c | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/c= hrome/cros_ec_typec.c > index 1ac5798d887f..6ee182101bc9 100644 > --- a/drivers/platform/chrome/cros_ec_typec.c > +++ b/drivers/platform/chrome/cros_ec_typec.c > @@ -311,6 +311,7 @@ static int cros_typec_register_port_altmodes(struct c= ros_typec_data *typec, > memset(&desc, 0, sizeof(desc)); > desc.svid =3D USB_TYPEC_TBT_SID; > desc.mode =3D TBT_MODE; > + desc.inactive =3D true; > amode =3D cros_typec_register_thunderbolt(port, &desc); > if (IS_ERR(amode)) > return PTR_ERR(amode); > --=20 > 2.47.1.613.gc27f4b7a9f-goog >=20 --W8cAO6hx+FSI0lHc Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQCtZK6p/AktxXfkOlzbaomhzOwwgUCZ2N3tgAKCRBzbaomhzOw woI7AP4m7+qsKf6OdfCv5MTSwIwsD2yr+IwtWh+s50egADVb0AEAh+bZVfhhc7KK CacGzufNf3FY6eEErPLaAfAFZ27aDAQ= =/0op -----END PGP SIGNATURE----- --W8cAO6hx+FSI0lHc--