[PATCH 0/2] Add SpacemiT K1 USB3.0 host controller support

[PATCH 0/2] Add SpacemiT K1 USB3.0 host controller support

[Ze Huang]

This patchset adds initial support for the USB 3.0 Dual-Role Device (DRD)
controller[1] found in the SpacemiT K1 SoC. The controller is based on Synopsys
DesignWare Core USB 3 (DWC3) IP, which already has mainline driver support.

The DWC3 controller on SpacemiT K1 supports both Host and Device modes for
USB 3.0 and USB 2.0, including High-Speed, Full-Speed, and Low-Speed operations.

The PHY interfaces required for the K1 USB subsystem, PIPE3 (for USB 3.0)
and UTMI+ (for USB 2.0) have already been supported in a previous patchset[2].

This patchset is based on 6.15-rc1. Tested on BananaPi and Jupiter board.

Link: https://developer.spacemit.com/documentation?token=AjHDwrW78igAAEkiHracBI9HnTb [1]
Link: https://lore.kernel.org/linux-riscv/20250418-b4-k1-usb3-phy-v2-v2-0-b69e02da84eb@whut.edu.cn [2]

Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
Changes in v2:
- dt-bindings:
  - add missing 'maxItems'
  - remove 'status' property in exmaple
  - fold dwc3 node into parent
- drop dwc3 glue driver and use snps,dwc3 driver directly
- rename dts nodes and reorder properties to fit coding style

---
Ze Huang (2):
      dt-bindings: usb: dwc3: add support for SpacemiT K1
      riscv: dts: spacemit: add usb3.0 support for K1

 .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml  | 95 ++++++++++++++++++++++
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts    | 52 ++++++++++++
 arch/riscv/boot/dts/spacemit/k1.dtsi               | 56 +++++++++++++
 3 files changed, 203 insertions(+)
---
base-commit: 64e9fdfc89a76fed38d8ddeed72d42ec71957ed9
change-id: 20250428-b4-k1-dwc3-v2-519e84a1b2cb
prerequisite-message-id: <20250416135406.16284-1-heylenay@4d2.org>
prerequisite-patch-id: 19b7f061557b184b9565e10ccfc0aab5754dfa73
prerequisite-patch-id: a56183c8b71a141ca6f5d401b67a5456f40d4a9c
prerequisite-patch-id: a4a3c44d4c3e44f5209bff2b2bd0b49cd5a9eebe
prerequisite-patch-id: 471fe02daa5297e85e9cee8dfef873375a348e9f
prerequisite-patch-id: 717bc3d50f0924f7697312cb78280b15a029ce2c
prerequisite-patch-id: 585a2a9ce37a5e2a036f7351ff8ff4ed859bbe3e
prerequisite-message-id: <20250418145401.2603648-1-elder@riscstar.com>
prerequisite-patch-id: a7769b6451bfd80d5e5366013753c5fc870b2255
prerequisite-patch-id: 8a8d0eefd0b4423d87f3c093b451a0fa60622ec4
prerequisite-patch-id: 30f92f93e5b3577bde61424303f21c709a715ec5
prerequisite-patch-id: d774b8281b5c6a822445365ee94925e1ab6c7a93
prerequisite-patch-id: 54a4f5d065eb9f212fd99efec6e7e06abbb9bad8
prerequisite-patch-id: 93962be60d1b58a98d947edf51b4af9edf513785
prerequisite-patch-id: 5f53f8bf16fb067628092daebc4831293261aa01
prerequisite-message-id: <CACRpkdZ6A0xORRQBnNNPFcNHg3xL=U3_xAcePmaDN3_ZYMzsaA@mail.gmail.com>
prerequisite-patch-id: a5d0181eb076c06b2147fb44a2400706bcad1ee3
prerequisite-patch-id: 59a37da7d2319858de1779e1b60e5362a102cf24
prerequisite-patch-id: a2fbaeda08eabbafcde1c9893dc82eddaef8f1b2
prerequisite-patch-id: f44247679d46a51c242703eca370ce0e3db2e61f
prerequisite-patch-id: 9d4cd8be42a37798815d0aaae21d3c022f815414

Best regards,
-- 
Ze Huang <huangze@whut.edu.cn>

[PATCH 1/2] dt-bindings: usb: dwc3: add support for SpacemiT K1

[Ze Huang]

Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
in
the SpacemiT K1 SoC. The controller is based on the Synopsys DesignWare
Core USB 3 (DWC3) IP, supporting both Host and Device modes for USB 3.0
and USB 2.0 standards.

Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
 .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml  | 95 ++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..5aece388900fa5bda9acb19add658310064bef8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
+
+maintainers:
+  - Ze Huang <huangze@whut.edu.cn>
+
+description: |
+  The SpacemiT K1 embeds a DWC3 USB IP Core which supports both Host and Device
+  functions for USB 3.0 and USB 2.0 standards.
+
+  Key features:
+  - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
+  - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
+  - Internal DMA controller and flexible endpoint FIFO sizing
+
+  Communication Interface:
+  - Use of PIPE3 (125MHz) interface for USB3.0 PHY
+  - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
+
+  The common content of the node is defined in snps,dwc3.yaml.
+
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - spacemit,k1-dwc3
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - spacemit,k1-dwc3
+      - const: snps,dwc3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: bus_early
+
+  resets:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 1
+    description:
+      On SpacemiT K1, USB performs DMA through bus other than parent DT node.
+      The 'interconnects' property explicitly describes this path, ensuring
+      correct address translation.
+
+  interconnect-names:
+    const: dma-mem
+
+  vbus-supply:
+    description: A phandle to the regulator supplying the VBUS voltage.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - interrupts
+  - interconnects
+  - interconnect-names
+
+additionalProperties: false
+
+examples:
+  - |
+    usb@c0a00000 {
+        compatible = "spacemit,k1-dwc3", "snps,dwc3";
+        reg = <0xc0a00000 0x10000>;
+        clocks = <&syscon_apmu 16>;
+        clock-names = "bus_early";
+        resets = <&syscon_apmu 8>;
+        interrupt-parent = <&plic>;
+        interrupts = <125>;
+        interconnects = <&dram_range0>;
+        interconnect-names = "dma-mem";
+    };

-- 
2.49.0

Re: [PATCH 1/2] dt-bindings: usb: dwc3: add support for SpacemiT K1

[Rob Herring (Arm)]

On Mon, 28 Apr 2025 15:38:11 +0800, Ze Huang wrote:
> Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
> in
> the SpacemiT K1 SoC. The controller is based on the Synopsys DesignWare
> Core USB 3 (DWC3) IP, supporting both Host and Device modes for USB 3.0
> and USB 2.0 standards.
> 
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
>  .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml  | 95 ++++++++++++++++++++++
>  1 file changed, 95 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.example.dtb: usb@c0a00000 (spacemit,k1-dwc3): Unevaluated properties are not allowed ('interconnect-names', 'interconnects' were unexpected)
	from schema $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250428-b4-k1-dwc3-v2-v1-1-7cb061abd619@whut.edu.cn

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH 2/2] riscv: dts: spacemit: add usb3.0 support for K1

[Ze Huang]

Add USB 3.0 support for the SpacemiT K1 SoC, including the
following components:

- USB 2.0 PHY nodes
- USB 3.0 combo PHY node
- USB 3.0 host controller
- USB 3.0 hub and vbus regulator (usb3_vhub, usb3_vbus)
- DRAM interconnect node for USB DMA ("dma-mem")

The `usb3_vbus` and `usb3_vhub` regulator node provides a fixed 5V
supply to power the onboard USB 3.0 hub and usb vbus.

On K1, some DMA transfers from devices to memory use separate buses with
different DMA address translation rules from the parent node. We express
this relationship through the interconnects node("dma-mem").

Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 52 +++++++++++++++++++++++
 arch/riscv/boot/dts/spacemit/k1.dtsi            | 56 +++++++++++++++++++++++++
 2 files changed, 108 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 816ef1bc358ec490aff184d5915d680dbd9f00cb..0c0bf572d31e056955eb2ff377c3262271dcc156 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -28,6 +28,25 @@ led1 {
 			default-state = "on";
 		};
 	};
+
+	usb3_vhub: regulator-vhub-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "USB30_VHUB";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	usb3_vbus: regulator-vbus-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "USB30_VBUS";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 };
 
 &uart0 {
@@ -35,3 +54,36 @@ &uart0 {
 	pinctrl-0 = <&uart0_2_cfg>;
 	status = "okay";
 };
+
+&usbphy2 {
+	status = "okay";
+};
+
+&combphy {
+	status = "okay";
+};
+
+&usb_dwc3 {
+	dr_mode = "host";
+	phy_type = "utmi";
+	snps,hsphy_interface = "utmi";
+	snps,dis_enblslpm_quirk;
+	snps,dis-u1u2-quirk;
+	snps,dis-u2-freeclk-exists-quirk;
+	snps,dis-del-phy-power-chg-quirk;
+	snps,dis_u2_susphy_quirk;
+	snps,dis_u3_susphy_quirk;
+	snps,dis_rxdet_inp3_quirk;
+	snps,xhci-trb-ent-quirk;
+	vbus-supply = <&usb3_vbus>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	hub@1 {
+		compatible = "usb2109,817";
+		reg = <0x1>;
+		vdd-supply = <&usb3_vhub>;
+		reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+	};
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index c0cc4b99c9356d550a470291dba9f2625b10f8df..c7b86c850da969e5412ad42c63995cd20b4d0484 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -4,6 +4,8 @@
  */
 
 #include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 /dts-v1/;
 / {
@@ -346,6 +348,13 @@ soc {
 		dma-noncoherent;
 		ranges;
 
+		dram_range0: dram-range@0 {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+			#interconnect-cells = <0>;
+		};
+
 		syscon_rcpu: system-controller@c0880000 {
 			compatible = "spacemit,k1-syscon-rcpu";
 			reg = <0x0 0xc0880000 0x0 0x2048>;
@@ -358,6 +367,53 @@ syscon_rcpu2: system-controller@c0888000 {
 			#reset-cells = <1>;
 		};
 
+		usb_dwc3: usb@c0a00000 {
+			compatible = "spacemit,k1-dwc3", "snps,dwc3";
+			reg = <0x0 0xc0a00000 0x0 0x10000>;
+			clocks = <&syscon_apmu CLK_USB30>;
+			clock-names = "bus_early";
+			resets = <&syscon_apmu RESET_USB3_0>;
+			interrupt-parent = <&plic>;
+			interrupts = <125>;
+			interconnects = <&dram_range0>;
+			interconnect-names = "dma-mem";
+			phys = <&usbphy2>, <&combphy PHY_TYPE_USB3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			status = "disabled";
+		};
+
+		usbphy0: phy@c0940000 {
+			compatible = "spacemit,usb2-phy";
+			reg = <0x0 0xc0940000 0x0 0x200>;
+			clocks = <&syscon_apmu CLK_USB_AXI>;
+			status = "disabled";
+		};
+
+		usbphy1: phy@c09c0000 {
+			compatible = "spacemit,usb2-phy";
+			reg = <0x0 0xc09c0000 0x0 0x200>;
+			clocks = <&syscon_apmu CLK_USB_P1>;
+			status = "disabled";
+		};
+
+		usbphy2: phy@0xc0a30000 {
+			compatible = "spacemit,k1-usb2-phy";
+			reg = <0x0 0xc0a30000 0x0 0x200>;
+			clocks = <&syscon_apmu CLK_USB30>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		combphy: phy@c0b10000 {
+			compatible = "spacemit,k1-combphy";
+			reg = <0x0 0xc0b10000 0x0 0x800>,
+			      <0x0 0xd4282910 0x0 0x400>;
+			reg-names = "ctrl", "sel";
+			resets = <&syscon_apmu RESET_PCIE0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
 		syscon_apbc: system-control@d4015000 {
 			compatible = "spacemit,k1-syscon-apbc";
 			reg = <0x0 0xd4015000 0x0 0x1000>;

-- 
2.49.0

Re: [PATCH 2/2] riscv: dts: spacemit: add usb3.0 support for K1

[Ze Huang]

Hi all,

I found some mistakes in the patch


I will correct them in next version.
Sorry for the confusion and thanks for your review!


On 4/28/25 3:38 PM, Ze Huang wrote:
> Add USB 3.0 support for the SpacemiT K1 SoC, including the
> following components:
...
> +
> +		usbphy0: phy@c0940000 {
> +			compatible = "spacemit,usb2-phy";

compatible = "spacemit,k1-usb2-phy ";

> +			reg = <0x0 0xc0940000 0x0 0x200>;
> +			clocks = <&syscon_apmu CLK_USB_AXI>;
> +			status = "disabled";
> +		};
> +
> +		usbphy1: phy@c09c0000 {
> +			compatible = "spacemit,usb2-phy";

compatible = "spacemit,k1-usb2-phy ";

> +			reg = <0x0 0xc09c0000 0x0 0x200>;
> +			clocks = <&syscon_apmu CLK_USB_P1>;
> +			status = "disabled";
> +		};
> +
> +		usbphy2: phy@0xc0a30000 {

usbphy2: phy@c0a30000 {

Re: [PATCH 2/2] riscv: dts: spacemit: add usb3.0 support for K1

[Yao Zi]

On Mon, Apr 28, 2025 at 03:38:12PM +0800, Ze Huang wrote:
> Add USB 3.0 support for the SpacemiT K1 SoC, including the
> following components:
> 
> - USB 2.0 PHY nodes
> - USB 3.0 combo PHY node
> - USB 3.0 host controller
> - USB 3.0 hub and vbus regulator (usb3_vhub, usb3_vbus)
> - DRAM interconnect node for USB DMA ("dma-mem")
> 
> The `usb3_vbus` and `usb3_vhub` regulator node provides a fixed 5V
> supply to power the onboard USB 3.0 hub and usb vbus.
> 
> On K1, some DMA transfers from devices to memory use separate buses with
> different DMA address translation rules from the parent node. We express
> this relationship through the interconnects node("dma-mem").
> 
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
>  arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 52 +++++++++++++++++++++++
>  arch/riscv/boot/dts/spacemit/k1.dtsi            | 56 +++++++++++++++++++++++++
>  2 files changed, 108 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> index 816ef1bc358ec490aff184d5915d680dbd9f00cb..0c0bf572d31e056955eb2ff377c3262271dcc156 100644
> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
> @@ -28,6 +28,25 @@ led1 {
>  			default-state = "on";
>  		};
>  	};
> +
> +	usb3_vhub: regulator-vhub-5v {
> +		compatible = "regulator-fixed";
> +		regulator-name = "USB30_VHUB";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +
> +	usb3_vbus: regulator-vbus-5v {
> +		compatible = "regulator-fixed";
> +		regulator-name = "USB30_VBUS";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		regulator-always-on;
> +		gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
>  };
>  
>  &uart0 {
> @@ -35,3 +54,36 @@ &uart0 {
>  	pinctrl-0 = <&uart0_2_cfg>;
>  	status = "okay";
>  };
> +
> +&usbphy2 {
> +	status = "okay";
> +};
> +
> +&combphy {
> +	status = "okay";
> +};
> +
> +&usb_dwc3 {
> +	dr_mode = "host";
> +	phy_type = "utmi";
> +	snps,hsphy_interface = "utmi";
> +	snps,dis_enblslpm_quirk;
> +	snps,dis-u1u2-quirk;
> +	snps,dis-u2-freeclk-exists-quirk;
> +	snps,dis-del-phy-power-chg-quirk;
> +	snps,dis_u2_susphy_quirk;
> +	snps,dis_u3_susphy_quirk;
> +	snps,dis_rxdet_inp3_quirk;
> +	snps,xhci-trb-ent-quirk;

I suspect whether it's the correct place to put these quirks: they look
like IP quirks which are present in every K1 SoC regardless of the
board model, if my understanding is correct they should go into SoC
devicetree.

> +	vbus-supply = <&usb3_vbus>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	hub@1 {
> +		compatible = "usb2109,817";
> +		reg = <0x1>;
> +		vdd-supply = <&usb3_vhub>;
> +		reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
> +	};
> +};
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index c0cc4b99c9356d550a470291dba9f2625b10f8df..c7b86c850da969e5412ad42c63995cd20b4d0484 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -4,6 +4,8 @@
>   */
>  
>  #include <dt-bindings/clock/spacemit,k1-syscon.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/phy/phy.h>
>  
>  /dts-v1/;
>  / {
> @@ -346,6 +348,13 @@ soc {
>  		dma-noncoherent;
>  		ranges;
>  
> +		dram_range0: dram-range@0 {
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
> +			#interconnect-cells = <0>;
> +		};
> +
>  		syscon_rcpu: system-controller@c0880000 {
>  			compatible = "spacemit,k1-syscon-rcpu";
>  			reg = <0x0 0xc0880000 0x0 0x2048>;
> @@ -358,6 +367,53 @@ syscon_rcpu2: system-controller@c0888000 {
>  			#reset-cells = <1>;
>  		};
>  
> +		usb_dwc3: usb@c0a00000 {
> +			compatible = "spacemit,k1-dwc3", "snps,dwc3";
> +			reg = <0x0 0xc0a00000 0x0 0x10000>;
> +			clocks = <&syscon_apmu CLK_USB30>;
> +			clock-names = "bus_early";
> +			resets = <&syscon_apmu RESET_USB3_0>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <125>;
> +			interconnects = <&dram_range0>;
> +			interconnect-names = "dma-mem";
> +			phys = <&usbphy2>, <&combphy PHY_TYPE_USB3>;
> +			phy-names = "usb2-phy", "usb3-phy";
> +			status = "disabled";
> +		};
> +
> +		usbphy0: phy@c0940000 {
> +			compatible = "spacemit,usb2-phy";
> +			reg = <0x0 0xc0940000 0x0 0x200>;
> +			clocks = <&syscon_apmu CLK_USB_AXI>;
> +			status = "disabled";
> +		};
> +
> +		usbphy1: phy@c09c0000 {
> +			compatible = "spacemit,usb2-phy";
> +			reg = <0x0 0xc09c0000 0x0 0x200>;
> +			clocks = <&syscon_apmu CLK_USB_P1>;
> +			status = "disabled";
> +		};

Why don't add #phy-cells properties to usbphy{0,1} just like usbphy2?
You've claimed #phy-cells as an essential property of
spacemit,k1-usb2-phy nodes in the PHY series and I suspect whether this
passes dtbs_check.

> +		usbphy2: phy@0xc0a30000 {
> +			compatible = "spacemit,k1-usb2-phy";
> +			reg = <0x0 0xc0a30000 0x0 0x200>;
> +			clocks = <&syscon_apmu CLK_USB30>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		combphy: phy@c0b10000 {
> +			compatible = "spacemit,k1-combphy";
> +			reg = <0x0 0xc0b10000 0x0 0x800>,
> +			      <0x0 0xd4282910 0x0 0x400>;
> +			reg-names = "ctrl", "sel";
> +			resets = <&syscon_apmu RESET_PCIE0>;
> +			#phy-cells = <1>;
> +			status = "disabled";
> +		};
> +
>  		syscon_apbc: system-control@d4015000 {
>  			compatible = "spacemit,k1-syscon-apbc";
>  			reg = <0x0 0xd4015000 0x0 0x1000>;
> 
> -- 
> 2.49.0
> 
> 

Best regards,
Yao Zi

Re: [PATCH 2/2] riscv: dts: spacemit: add usb3.0 support for K1

[Ze Huang]

On 4/28/25 4:24 PM, Yao Zi wrote:
> On Mon, Apr 28, 2025 at 03:38:12PM +0800, Ze Huang wrote:
>> Add USB 3.0 support for the SpacemiT K1 SoC, including the
>> following components:
>>
>> - USB 2.0 PHY nodes
>> - USB 3.0 combo PHY node
>> - USB 3.0 host controller
>> - USB 3.0 hub and vbus regulator (usb3_vhub, usb3_vbus)
>> - DRAM interconnect node for USB DMA ("dma-mem")
>>
>> The `usb3_vbus` and `usb3_vhub` regulator node provides a fixed 5V
>> supply to power the onboard USB 3.0 hub and usb vbus.
>>
>> On K1, some DMA transfers from devices to memory use separate buses with
>> different DMA address translation rules from the parent node. We express
>> this relationship through the interconnects node("dma-mem").
>>
>> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
>> ---
>>   arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 52 +++++++++++++++++++++++
>>   arch/riscv/boot/dts/spacemit/k1.dtsi            | 56 +++++++++++++++++++++++++
>>   2 files changed, 108 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
>> index 816ef1bc358ec490aff184d5915d680dbd9f00cb..0c0bf572d31e056955eb2ff377c3262271dcc156 100644
>> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
>> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
>> @@ -28,6 +28,25 @@ led1 {
>>   			default-state = "on";
>>   		};
>>   	};
>> +
>> +	usb3_vhub: regulator-vhub-5v {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "USB30_VHUB";
>> +		regulator-min-microvolt = <5000000>;
>> +		regulator-max-microvolt = <5000000>;
>> +		gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
>> +		enable-active-high;
>> +	};
>> +
>> +	usb3_vbus: regulator-vbus-5v {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "USB30_VBUS";
>> +		regulator-min-microvolt = <5000000>;
>> +		regulator-max-microvolt = <5000000>;
>> +		regulator-always-on;
>> +		gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
>> +		enable-active-high;
>> +	};
>>   };
>>   
>>   &uart0 {
>> @@ -35,3 +54,36 @@ &uart0 {
>>   	pinctrl-0 = <&uart0_2_cfg>;
>>   	status = "okay";
>>   };
>> +
>> +&usbphy2 {
>> +	status = "okay";
>> +};
>> +
>> +&combphy {
>> +	status = "okay";
>> +};
>> +
>> +&usb_dwc3 {
>> +	dr_mode = "host";
>> +	phy_type = "utmi";
>> +	snps,hsphy_interface = "utmi";
>> +	snps,dis_enblslpm_quirk;
>> +	snps,dis-u1u2-quirk;
>> +	snps,dis-u2-freeclk-exists-quirk;
>> +	snps,dis-del-phy-power-chg-quirk;
>> +	snps,dis_u2_susphy_quirk;
>> +	snps,dis_u3_susphy_quirk;
>> +	snps,dis_rxdet_inp3_quirk;
>> +	snps,xhci-trb-ent-quirk;
> I suspect whether it's the correct place to put these quirks: they look
> like IP quirks which are present in every K1 SoC regardless of the
> board model, if my understanding is correct they should go into SoC
> devicetree.

I checked these quirks in differenct board dts in vendor repo, they are 
actually the same.
Will follow.

>
>> +	vbus-supply = <&usb3_vbus>;
>> +	#address-cells = <1>;
>> +	#size-cells = <0>;
>> +	status = "okay";
>> +
>> +	hub@1 {
>> +		compatible = "usb2109,817";
>> +		reg = <0x1>;
>> +		vdd-supply = <&usb3_vhub>;
>> +		reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
>> +	};
>> +};
>> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
>> index c0cc4b99c9356d550a470291dba9f2625b10f8df..c7b86c850da969e5412ad42c63995cd20b4d0484 100644
>> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
>> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
>> @@ -4,6 +4,8 @@
>>    */
>>   
>>   #include <dt-bindings/clock/spacemit,k1-syscon.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/phy/phy.h>
>>   
>>   /dts-v1/;
>>   / {
>> @@ -346,6 +348,13 @@ soc {
>>   		dma-noncoherent;
>>   		ranges;
>>   
>> +		dram_range0: dram-range@0 {
>> +			#address-cells = <2>;
>> +			#size-cells = <2>;
>> +			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
>> +			#interconnect-cells = <0>;
>> +		};
>> +
>>   		syscon_rcpu: system-controller@c0880000 {
>>   			compatible = "spacemit,k1-syscon-rcpu";
>>   			reg = <0x0 0xc0880000 0x0 0x2048>;
>> @@ -358,6 +367,53 @@ syscon_rcpu2: system-controller@c0888000 {
>>   			#reset-cells = <1>;
>>   		};
>>   
>> +		usb_dwc3: usb@c0a00000 {
>> +			compatible = "spacemit,k1-dwc3", "snps,dwc3";
>> +			reg = <0x0 0xc0a00000 0x0 0x10000>;
>> +			clocks = <&syscon_apmu CLK_USB30>;
>> +			clock-names = "bus_early";
>> +			resets = <&syscon_apmu RESET_USB3_0>;
>> +			interrupt-parent = <&plic>;
>> +			interrupts = <125>;
>> +			interconnects = <&dram_range0>;
>> +			interconnect-names = "dma-mem";
>> +			phys = <&usbphy2>, <&combphy PHY_TYPE_USB3>;
>> +			phy-names = "usb2-phy", "usb3-phy";
>> +			status = "disabled";
>> +		};
>> +
>> +		usbphy0: phy@c0940000 {
>> +			compatible = "spacemit,usb2-phy";
>> +			reg = <0x0 0xc0940000 0x0 0x200>;
>> +			clocks = <&syscon_apmu CLK_USB_AXI>;
>> +			status = "disabled";
>> +		};
>> +
>> +		usbphy1: phy@c09c0000 {
>> +			compatible = "spacemit,usb2-phy";
>> +			reg = <0x0 0xc09c0000 0x0 0x200>;
>> +			clocks = <&syscon_apmu CLK_USB_P1>;
>> +			status = "disabled";
>> +		};
> Why don't add #phy-cells properties to usbphy{0,1} just like usbphy2?
> You've claimed #phy-cells as an essential property of
> spacemit,k1-usb2-phy nodes in the PHY series and I suspect whether this
> passes dtbs_check.

The DT bindings for the USB PHY were submitted in an earlier patchset,
some dts checks about PHY were missed.

I will add #phy-cells in next version. thanks!

>
>> +		usbphy2: phy@0xc0a30000 {
>> +			compatible = "spacemit,k1-usb2-phy";
>> +			reg = <0x0 0xc0a30000 0x0 0x200>;
>> +			clocks = <&syscon_apmu CLK_USB30>;
>> +			#phy-cells = <0>;
>> +			status = "disabled";
>> +		};
>> +
>> +		combphy: phy@c0b10000 {
>> +			compatible = "spacemit,k1-combphy";
>> +			reg = <0x0 0xc0b10000 0x0 0x800>,
>> +			      <0x0 0xd4282910 0x0 0x400>;
>> +			reg-names = "ctrl", "sel";
>> +			resets = <&syscon_apmu RESET_PCIE0>;
>> +			#phy-cells = <1>;
>> +			status = "disabled";
>> +		};
>> +
>>   		syscon_apbc: system-control@d4015000 {
>>   			compatible = "spacemit,k1-syscon-apbc";
>>   			reg = <0x0 0xd4015000 0x0 0x1000>;
>>
>> -- 
>> 2.49.0
>>
>>
> Best regards,
> Yao Zi
>
>
>