Re: [PATCH 2/2] usb: mtu3: Add MT8195 MTU3 ip-sleep wakeup support

Matthias Brugger
2024-01-22T07:58:43Z

On 12/01/2024 14:32, AngeloGioacchino Del Regno wrote:
> Add support for the ip-sleep wakeup functionality on the three MTU3
> controllers found on the MT8195 SoC.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/usb/mtu3/mtu3_host.c | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/usb/mtu3/mtu3_host.c b/drivers/usb/mtu3/mtu3_host.c
> index 9f2be22af844..85f49e00e8db 100644
> --- a/drivers/usb/mtu3/mtu3_host.c
> +++ b/drivers/usb/mtu3/mtu3_host.c
> @@ -34,6 +34,19 @@
> #define WC0_SSUSB0_CDEN BIT(6)
> #define WC0_IS_SPM_EN BIT(1)
>
> +/* mt8195 */
> +#define PERI_WK_CTRL0_8195 0x04
> +#define WC0_IS_P_95 BIT(30) /* polarity */
> +#define WC0_IS_C_95(x) ((u32)(((x) & 0x7) << 27))
> +#define WC0_IS_EN_P3_95 BIT(26)
> +#define WC0_IS_EN_P2_95 BIT(25)
> +#define WC0_IS_EN_P1_95 BIT(24)

Not used, shouldn't we drop that?

Regards,
Matthias

> +
> +#define PERI_WK_CTRL1_8195 0x20
> +#define WC1_IS_C_95(x) ((u32)(((x) & 0xf) << 28))
> +#define WC1_IS_P_95 BIT(12)
> +#define WC1_IS_EN_P0_95 BIT(6)
> +
> /* mt2712 etc */
> #define PERI_SSUSB_SPM_CTRL 0x0
> #define SSC_IP_SLEEP_EN BIT(4)
> @@ -44,6 +57,9 @@ enum ssusb_uwk_vers {
> SSUSB_UWK_V2,
> SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
> SSUSB_UWK_V1_2, /* specific revision 1.02 */
> + SSUSB_UWK_V1_3, /* mt8195 IP0 */
> + SSUSB_UWK_V1_5 = 105, /* mt8195 IP2 */
> + SSUSB_UWK_V1_6, /* mt8195 IP3 */
> };
>
> /*
> @@ -70,6 +86,21 @@ static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable)
> msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
> val = enable ? msk : 0;
> break;
> + case SSUSB_UWK_V1_3:
> + reg = ssusb->uwk_reg_base + PERI_WK_CTRL1_8195;
> + msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
> + val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
> + break;
> + case SSUSB_UWK_V1_5:
> + reg = ssusb->uwk_reg_base + PERI_WK_CTRL0_8195;
> + msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
> + val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
> + break;
> + case SSUSB_UWK_V1_6:
> + reg = ssusb->uwk_reg_base + PERI_WK_CTRL0_8195;
> + msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
> + val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
> + break;
> case SSUSB_UWK_V2:
> reg = ssusb->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
> msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;