Re: [PATCH v9 0/5] Support system sleep with offloaded usb transfers

[Pierre-Louis Bossart <pierre-louis.bossart@linux.dev>]

>>> 2. Power Management Adjustment:  Modifications to the USB driver stack
>>> (dwc3 controller driver, xhci host controller driver, and USB device
>>> drivers) allow the system to sleep without disrupting co-processor managed
>>> USB transfers. This involves adding conditional checks to bypass some
>>> power management operations.
>>
>> This is even more confusing, initially the point was to prevent the controller from sleeping while there are offloaded transactions, but now the goal would be to allow the system to sleep while there are offloaded transactions. This isn't the same problem, is it?
>>
> 
> The purpose of this series is to allow offloaded usb transfers happen
> during system sleep. In order to achieve this, we need to prevent the
> controller from sleeping when there's offloaded usb transfer ongoing,
> specifically when the system is sleeping.
> Without this series, the system could still allow offloaded usb
> traffic when the system is active, but the system would put the
> controller to sleep when the system is going to sleep, thus we're not
> able to suspend the system when we have offloaded usb transfers in the
> current system.

I am not following, sorry.

Is the desired outcome to 

a) prevent the system from entering S3 if there is an active USB audio offloaded stream?

or b) allow offloaded transactions even when the system is in S3?


which is it?

a) would be rather interesting, but currently we don't have any such behavior supported. When the system enters S3 all audio stops. The stream will resume when the system goes back to S0. Do we really want the battery to drain in S3?

b) seems rather complicated, once the on-going DMA transfers complete then who's going to refill buffers for the USB offloaded streams? Allowing the lowest level to operate even in S3 is only a small part of the puzzle, someone's got to provide data at some point. Unless the data is generated also by a side DSP having access to mass storage or wireless interfaces?