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[77.252.46.238]) by smtp.gmail.com with ESMTPSA id w26-20020a50fa9a000000b0052a401d8ef6sm6759359edr.71.2023.09.04.23.53.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Sep 2023 23:53:42 -0700 (PDT) Message-ID: Date: Tue, 5 Sep 2023 08:53:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH 5/5] phy: qcom-qmp-usb: Add Qualcomm SDX75 USB3 PHY support Content-Language: en-US To: Rohit Agarwal , agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, abel.vesa@linaro.org, quic_wcheng@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, kernel@quicinc.com References: <1693889028-6485-1-git-send-email-quic_rohiagar@quicinc.com> <1693889028-6485-6-git-send-email-quic_rohiagar@quicinc.com> From: Krzysztof Kozlowski In-Reply-To: <1693889028-6485-6-git-send-email-quic_rohiagar@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org On 05/09/2023 06:43, Rohit Agarwal wrote: > Add support for USB3 QMP PHY found in SDX75 platform. > > Signed-off-by: Rohit Agarwal > --- > > +static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = { > + .lanes = 1, > + .offsets = &qmp_usb_offsets_v5, > + > + .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl, > + .serdes_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl), > + .tx_tbl = sdx75_usb3_uniphy_tx_tbl, > + .tx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl), > + .rx_tbl = sdx75_usb3_uniphy_rx_tbl, > + .rx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl), > + .pcs_tbl = sdx75_usb3_uniphy_pcs_tbl, > + .pcs_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl), > + .pcs_usb_tbl = sdx75_usb3_uniphy_pcs_usb_tbl, > + .pcs_usb_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl), > + .clk_list = qmp_v4_sdx55_usbphy_clk_l, > + .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), > + .reset_list = msm8996_usb3phy_reset_l, > + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), > + .vreg_list = qmp_phy_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > + .regs = qmp_v5_usb3phy_regs_layout, > + .pcs_usb_offset = 0x1000, > + > + .has_pwrdn_delay = true, > + Stray blank line > +}; > + > static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { > .lanes = 2, > > @@ -1985,6 +2141,7 @@ static int qmp_usb_init(struct phy *phy) > void __iomem *dp_com = qmp->dp_com; > int ret; > > + No need for this. Best regards, Krzysztof