[2/3] usb: dwc3: Set reference clock period

[2/3] usb: dwc3: Set reference clock period

[Thinh Nguyen]

Get the reference clock period from the device property and reprogram it
during core power-on initialization.

Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
---
 drivers/usb/dwc3/core.c | 22 ++++++++++++++++++++++
 drivers/usb/dwc3/core.h | 10 ++++++++++
 2 files changed, 32 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index becfbb87f791..4437db4a1e15 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1001,6 +1001,26 @@ static int dwc3_core_init(struct dwc3 *dwc)
 		dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
 	}
 
+	if (dwc->refclk_period_ns) {
+		switch (dwc->refclk_period_ns) {
+		case DWC3_GUCTL_REFCLKPER_25NS:
+		case DWC3_GUCTL_REFCLKPER_41NS:
+		case DWC3_GUCTL_REFCLKPER_50NS:
+		case DWC3_GUCTL_REFCLKPER_52NS:
+		case DWC3_GUCTL_REFCLKPER_58NS:
+		case DWC3_GUCTL_REFCLKPER_62NS:
+			reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
+			reg &= ~DWC3_GUCTL_REFCLKPER(~0);
+			reg |= DWC3_GUCTL_REFCLKPER(dwc->refclk_period_ns);
+			dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
+			break;
+		default:
+			dev_err(dwc->dev, "Invalid refclk period: %dns\n",
+				dwc->refclk_period_ns);
+			break;
+		}
+	}
+
 	/*
 	 * Must config both number of packets and max burst settings to enable
 	 * RX and/or TX threshold.
@@ -1246,6 +1266,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
 				&hird_threshold);
 	dwc->usb3_lpm_capable = device_property_read_bool(dev,
 				"snps,usb3_lpm_capable");
+	device_property_read_u8(dev, "snps,refclk-period-ns",
+				&dwc->refclk_period_ns);
 	device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
 				&rx_thr_num_pkt_prd);
 	device_property_read_u8(dev, "snps,rx-max-burst-prd",
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 5bfb62533e0f..5ce985b2e6c7 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -240,6 +240,14 @@
 
 /* Global User Control Register */
 #define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
+#define DWC3_GUCTL_REFCLKPER(n)		(((n) & 0x3ff) << 22)
+
+#define DWC3_GUCTL_REFCLKPER_25NS	25
+#define DWC3_GUCTL_REFCLKPER_41NS	41
+#define DWC3_GUCTL_REFCLKPER_50NS	50
+#define DWC3_GUCTL_REFCLKPER_52NS	52
+#define DWC3_GUCTL_REFCLKPER_58NS	58
+#define DWC3_GUCTL_REFCLKPER_62NS	62
 
 /* Global User Control 1 Register */
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
@@ -991,6 +999,7 @@ struct dwc3_scratchpad_array {
  *			change quirk.
  * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
  *			check during HS transmit.
+ * @refclk_period_ns: reference clock period in nanoseconds.
  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
  * @tx_de_emphasis: Tx de-emphasis value
  * 	0	- -6dB de-emphasis
@@ -1129,6 +1138,7 @@ struct dwc3 {
 	u8			rx_max_burst_prd;
 	u8			tx_thr_num_pkt_prd;
 	u8			tx_max_burst_prd;
+	u8			refclk_period_ns;
 
 	const char		*hsphy_interface;