[PATCH v3 0/3] MediaTek MT8188 MTU3 USB and Genio 510/700 TypeC

[PATCH v3 0/3] MediaTek MT8188 MTU3 USB and Genio 510/700 TypeC

[AngeloGioacchino Del Regno]

This series adds MTU3 nodes to the MT8188 base devicetree, fixes the
Geralt Chromebooks to use it, and adds support for all of the USB
ports, including TypeC Power Delivery, Alternate Modes, etc, found
on the MediaTek Genio 510 and Genio 700 Evaluation Kits.

This also adds the missing SuperSpeed port to the mtk-xhci binding.

AngeloGioacchino Del Regno (3):
  dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP
  arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe
    USB
  arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX

 .../bindings/usb/mediatek,mtk-xhci.yaml       |   4 +
 .../boot/dts/mediatek/mt8188-geralt.dtsi      |  18 +++
 arch/arm64/boot/dts/mediatek/mt8188.dtsi      | 121 +++++++++-----
 .../dts/mediatek/mt8390-genio-common.dtsi     | 151 +++++++++++++++++-
 4 files changed, 251 insertions(+), 43 deletions(-)

-- 
2.48.1

[PATCH v3 1/3] dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP

[AngeloGioacchino Del Regno]

Add a port used to connect the SuperSpeed output endpoint to a
Type-C connector.

Note that the MediaTek XHCI controllers are always in front of a
different controller handling the USB HS (usually, MTU3), so the
only port that this controller provides is SuperSpeed, while the
HighSpeed one comes from elsewhere.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
index ef3143f4b794..004d3ebec091 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
@@ -106,6 +106,10 @@ properties:
       - description: USB3/SS(P) PHY
       - description: USB2/HS PHY
 
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description: Super Speed (SS) Output endpoint to a Type-C connector
+
   vusb33-supply:
     description: Regulator of USB AVDD3.3v
 
-- 
2.48.1

[PATCH v3 2/3] arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe USB

[AngeloGioacchino Del Regno]

The MT8188 SoC has three USB controllers, and all of them are behind
the MTU3 DRD controller.

Add the missing MTU3 nodes, default disabled, for all USB controllers
and move the related XHCI nodes to be children of their MTU3 DRD to
correctly describe the SoC.

In order to retain USB functionality on all of the MT8188 and MT8390
boards, also move the vusb33 supply and enable the relevant MTU3 nodes
with special attention to the MT8188 Geralt Chromebooks, where it was
necessary to set the dr_mode of all MTU3 controllers to host to avoid
interfering with the EC performing DRD on its own.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../boot/dts/mediatek/mt8188-geralt.dtsi      |  18 +++
 arch/arm64/boot/dts/mediatek/mt8188.dtsi      | 121 ++++++++++++------
 .../dts/mediatek/mt8390-genio-common.dtsi     |  28 ++++
 3 files changed, 125 insertions(+), 42 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
index b6abecbcfa81..faed5c8bc721 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
@@ -1103,6 +1103,12 @@ &u3phy2 {
 };
 
 /* USB detachable base */
+&ssusb0 {
+	dr_mode = "host";
+	vusb33-supply = <&pp3300_s3>;
+	status = "okay";
+};
+
 &xhci0 {
 	/* controlled by EC */
 	vbus-supply = <&pp3300_z1>;
@@ -1110,6 +1116,12 @@ &xhci0 {
 };
 
 /* USB3 hub */
+&ssusb1 {
+	dr_mode = "host";
+	vusb33-supply = <&pp3300_s3>;
+	status = "okay";
+};
+
 &xhci1 {
 	vusb33-supply = <&pp3300_s3>;
 	vbus-supply = <&pp5000_usb_vbus>;
@@ -1117,6 +1129,12 @@ &xhci1 {
 };
 
 /* USB BT */
+&ssusb2 {
+	dr_mode = "host";
+	vusb33-supply = <&pp3300_s3>;
+	status = "okay";
+};
+
 &xhci2 {
 	/* no power supply since MT7921's power is controlled by PCIe */
 	/* MT7921's USB BT has issues with USB2 LPM */
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index d2e1ff7236b1..c226998b7e47 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1649,6 +1649,38 @@ spi5: spi@11019000 {
 			status = "disabled";
 		};
 
+		ssusb1: usb@11201000 {
+			compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
+			reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			ranges = <0 0 0 0x11200000 0 0x3f00>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_TOP>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
+				 <&topckgen CLK_TOP_SSUSB_TOP_REF>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
+			clock-names = "sys_ck", "ref_ck", "mcu_ck";
+			phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x468 2>;
+			status = "disabled";
+
+			xhci1: usb@0 {
+				compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+				reg = <0 0 0 0x1000>;
+				reg-names = "mac";
+				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+				assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>;
+				assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+				clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
+				clock-names = "sys_ck";
+				status = "disabled";
+			};
+		};
+
 		eth: ethernet@11021000 {
 			compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",
 				     "snps,dwmac-5.10a";
@@ -1746,27 +1778,6 @@ queue3 {
 			};
 		};
 
-		xhci1: usb@11200000 {
-			compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x1000>,
-			      <0 0x11203e00 0 0x0100>;
-			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
-			phys = <&u2port1 PHY_TYPE_USB2>,
-			       <&u3port1 PHY_TYPE_USB3>;
-			assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
-					  <&topckgen CLK_TOP_SSUSB_XHCI>;
-			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
-						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
-			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
-				 <&topckgen CLK_TOP_SSUSB_TOP_REF>,
-				 <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
-			clock-names = "sys_ck", "ref_ck", "mcu_ck";
-			mediatek,syscon-wakeup = <&pericfg 0x468 2>;
-			wakeup-source;
-			status = "disabled";
-		};
-
 		mmc0: mmc@11230000 {
 			compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
 			reg = <0 0x11230000 0 0x10000>,
@@ -1867,42 +1878,68 @@ imp_iic_wrap_c: clock-controller@11283000 {
 			#clock-cells = <1>;
 		};
 
-		xhci2: usb@112a0000 {
-			compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
-			reg = <0 0x112a0000 0 0x1000>,
-			      <0 0x112a3e00 0 0x0100>;
+		ssusb2: usb@112a1000 {
+			compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
+			reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
 			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
-			phys = <&u2port2 PHY_TYPE_USB2>;
-			assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
-					  <&topckgen CLK_TOP_USB_TOP_3P>;
-			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
-						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			ranges = <0 0 0 0x112a0000 0 0x3f00>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
 			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
 				 <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>,
 				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck";
+			phys = <&u2port2 PHY_TYPE_USB2>;
+			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x470 2>;
 			status = "disabled";
+
+			xhci2: usb@0 {
+				compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+				reg = <0 0 0 0x1000>;
+				reg-names = "mac";
+				interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+				assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+				assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+				clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+				clock-names = "sys_ck";
+				status = "disabled";
+			};
 		};
 
-		xhci0: usb@112b0000 {
-			compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
-			reg = <0 0x112b0000 0 0x1000>,
-			      <0 0x112b3e00 0 0x0100>;
+		ssusb0: usb@112b1000 {
+			compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
+			reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
 			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
-			phys = <&u2port0 PHY_TYPE_USB2>;
-			assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
-					  <&topckgen CLK_TOP_USB_TOP_2P>;
-			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
-						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			ranges = <0 0 0 0x112b0000 0 0x3f00>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+			assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
 			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
 				 <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>,
 				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck";
-			mediatek,syscon-wakeup = <&pericfg 0x460 2>;
+			phys = <&u2port0 PHY_TYPE_USB2>;
 			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x460 2>;
 			status = "disabled";
+
+			xhci0: usb@0 {
+				compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+				reg = <0 0 0 0x1000>;
+				reg-names = "mac";
+				interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+				assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
+				assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+				clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
+				clock-names = "sys_ck";
+				status = "disabled";
+			};
 		};
 
 		pcie: pcie@112f0000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
index a37cf102a6e9..fd977daa4185 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
@@ -1011,13 +1011,25 @@ &u3phy2 {
 	status = "okay";
 };
 
+&ssusb0 {
+	dr_mode = "host";
+	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	status = "okay";
+};
+
 &xhci0 {
 	status = "okay";
+};
+
+&ssusb1 {
+	dr_mode = "host";
 	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	status = "okay";
 };
 
 &xhci1 {
 	status = "okay";
+	vdd-supply = <&usb_hub_fixed_3v3>;
 	vusb33-supply = <&mt6359_vusb_ldo_reg>;
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -1037,6 +1049,22 @@ hub_3_0: hub@2 {
 		reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
 		vdd-supply = <&usb_hub_fixed_3v3>;
 	};
+
+	port {
+		xhci_ss_ep: endpoint {
+			remote-endpoint = <&typec_con_ss>;
+		};
+	};
+};
+
+&ssusb2 {
+	interrupts-extended = <&gic GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>,
+			      <&pio 220 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "host", "wakeup";
+
+	dr_mode = "host";
+	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	status = "okay";
 };
 
 &xhci2 {
-- 
2.48.1

[PATCH v3 3/3] arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX

[AngeloGioacchino Del Regno]

This board features multiple USB connectors:
 * One Type-C connector with Power Delivery and Alt. Modes;
 * One MicroUSB connector, also used for bootloader SW download;
 * One USB through the RaspberryPi-compatible pins header.

Add configuration for the MTU3 controllers providing OTG support
with role switching both on the MicroUSB port, RPi pins header,
and the Type-C port found on this board.

Moreover, add the Richtek RT1715 Type-C Power Delivery Controller
which manages current source/sink, linked to the iTE IT5205 Type-C
Alternate Mode Passive Mux, handling both mode switching between
USB (up to 3.1 Gen2 10Gbps) and DisplayPort (four lanes, DP1.4,
op to 8.1Gbps) and plug orientation switching.

All USB ports reside on different controller instances, and all of
them support host or gadget and can be configured as desired at
runtime.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../dts/mediatek/mt8390-genio-common.dtsi     | 139 ++++++++++++++++--
 1 file changed, 130 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
index fd977daa4185..83828baa887b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
@@ -260,6 +260,22 @@ &i2c1 {
 	pinctrl-0 = <&i2c1_pins>;
 	clock-frequency = <400000>;
 	status = "okay";
+
+	typec-mux@48 {
+		compatible = "ite,it5205";
+		reg = <0x48>;
+
+		mode-switch;
+		orientation-switch;
+
+		vcc-supply = <&mt6359_vcn33_1_bt_ldo_reg>;
+
+		port {
+			it5205_sbu_mux: endpoint {
+				remote-endpoint = <&typec_sbu_out>;
+			};
+		};
+	};
 };
 
 &i2c2 {
@@ -281,6 +297,66 @@ &i2c4 {
 	pinctrl-0 = <&i2c4_pins>;
 	clock-frequency = <1000000>;
 	status = "okay";
+
+	rt1715@4e {
+		compatible = "richtek,rt1715";
+		reg = <0x4e>;
+		interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&tcpci_int_pins>;
+		vbus-supply = <&usb_p1_vbus>;
+
+		connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			op-sink-microwatt = <10000000>;
+			power-role = "dual";
+			try-power-role  = "sink";
+			pd-revision = /bits/ 8 <0x03 0x00 0x01 0x08>;
+
+			sink-pdos = <PDO_FIXED(5000, 2000,
+					       PDO_FIXED_DUAL_ROLE |
+					       PDO_FIXED_DATA_SWAP)>;
+			source-pdos = <PDO_FIXED(5000, 2000,
+						 PDO_FIXED_DUAL_ROLE |
+						 PDO_FIXED_DATA_SWAP)>;
+
+			altmodes {
+				displayport {
+					svid = /bits/ 16 <0xff01>;
+					vdo = <0x001c1c47>;
+				};
+			};
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					typec_con_hs: endpoint {
+						remote-endpoint = <&mtu3_hs1_role_sw>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					typec_con_ss: endpoint {
+						remote-endpoint = <&xhci_ss_ep>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					typec_sbu_out: endpoint {
+						remote-endpoint = <&it5205_sbu_mux>;
+					};
+
+				};
+			};
+		};
+	};
 };
 
 &i2c5 {
@@ -849,6 +925,14 @@ pins-reset {
 		};
 	};
 
+	tcpci_int_pins: tcpci-int-pins {
+		pins-int-n {
+			pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>;
+			bias-pull-up;
+			input-enable;
+		};
+	};
+
 	uart0_pins: uart0-pins {
 		pins {
 			pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
@@ -904,6 +988,14 @@ pins-usb-hub-3v3-en {
 		};
 	};
 
+	usb2_default_pins: usb2-default-pins {
+		pins-iddig {
+			pinmux = <PINMUX_GPIO89__FUNC_B_GPIO89>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
 	wifi_pwrseq_pins: wifi-pwrseq-pins {
 		pins-wifi-enable {
 			pinmux = <PINMUX_GPIO127__FUNC_B_GPIO127>;
@@ -1012,9 +1104,21 @@ &u3phy2 {
 };
 
 &ssusb0 {
-	dr_mode = "host";
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+	usb-role-switch;
+	wakeup-source;
 	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	pinctrl-0 = <&usb_default_pins>;
+	pinctrl-names = "default";
 	status = "okay";
+
+	connector {
+		compatible = "gpio-usb-b-connector", "usb-b-connector";
+		type = "micro";
+		id-gpios = <&pio 83 GPIO_ACTIVE_HIGH>;
+		vbus-supply = <&usb_p0_vbus>;
+	};
 };
 
 &xhci0 {
@@ -1022,14 +1126,23 @@ &xhci0 {
 };
 
 &ssusb1 {
-	dr_mode = "host";
+	dr_mode = "otg";
+	usb-role-switch;
+	wakeup-source;
 	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	pinctrl-0 = <&usb1_default_pins>;
+	pinctrl-names = "default";
 	status = "okay";
+
+	port {
+		mtu3_hs1_role_sw: endpoint {
+			remote-endpoint = <&typec_con_hs>;
+		};
+	};
 };
 
 &xhci1 {
 	status = "okay";
-	vdd-supply = <&usb_hub_fixed_3v3>;
 	vusb33-supply = <&mt6359_vusb_ldo_reg>;
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -1058,17 +1171,25 @@ xhci_ss_ep: endpoint {
 };
 
 &ssusb2 {
-	interrupts-extended = <&gic GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>,
-			      <&pio 220 IRQ_TYPE_LEVEL_HIGH>;
-	interrupt-names = "host", "wakeup";
-
-	dr_mode = "host";
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+	usb-role-switch;
 	vusb33-supply = <&mt6359_vusb_ldo_reg>;
+	wakeup-source;
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb2_default_pins>;
 	status = "okay";
+
+	connector {
+		compatible = "gpio-usb-b-connector", "usb-b-connector";
+		type = "micro";
+		id-gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+		vbus-supply = <&usb_p2_vbus>;
+	};
 };
 
 &xhci2 {
-	status = "okay";
 	vusb33-supply = <&mt6359_vusb_ldo_reg>;
 	vbus-supply = <&sdio_fixed_3v3>; /* wifi_3v3 */
+	status = "okay";
 };
-- 
2.48.1

Re: [PATCH v3 0/3] MediaTek MT8188 MTU3 USB and Genio 510/700 TypeC

[AngeloGioacchino Del Regno]

Il 20/02/25 11:55, AngeloGioacchino Del Regno ha scritto:
> This series adds MTU3 nodes to the MT8188 base devicetree, fixes the
> Geralt Chromebooks to use it, and adds support for all of the USB
> ports, including TypeC Power Delivery, Alternate Modes, etc, found
> on the MediaTek Genio 510 and Genio 700 Evaluation Kits.
> 
> This also adds the missing SuperSpeed port to the mtk-xhci binding.

Forgot to add....

Changes in v3:
  - Added a commit to allow the SuperSpeed port in mtk-xhci, resolving
    dtbs_check failures
  - Removed useless vdd-supply from xhci1 in mt8390-genio-common.dtsi
  - Removed useless interrupts-extended, as the wakeup interrupt cannot
    be found anywhere in the schematics; the wakeup anyway works because
    of the pericfg's syscon-wakeup doing the same job.

Cheers!

> 
> AngeloGioacchino Del Regno (3):
>    dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP
>    arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe
>      USB
>    arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX
> 
>   .../bindings/usb/mediatek,mtk-xhci.yaml       |   4 +
>   .../boot/dts/mediatek/mt8188-geralt.dtsi      |  18 +++
>   arch/arm64/boot/dts/mediatek/mt8188.dtsi      | 121 +++++++++-----
>   .../dts/mediatek/mt8390-genio-common.dtsi     | 151 +++++++++++++++++-
>   4 files changed, 251 insertions(+), 43 deletions(-)
> 

Re: [PATCH v3 1/3] dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 557 bytes --]

On Thu, Feb 20, 2025 at 11:55:12AM +0100, AngeloGioacchino Del Regno wrote:
> Add a port used to connect the SuperSpeed output endpoint to a
> Type-C connector.
> 
> Note that the MediaTek XHCI controllers are always in front of a
> different controller handling the USB HS (usually, MTU3), so the
> only port that this controller provides is SuperSpeed, while the
> HighSpeed one comes from elsewhere.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v3 0/3] MediaTek MT8188 MTU3 USB and Genio 510/700 TypeC

[Rob Herring (Arm)]

On Thu, 20 Feb 2025 11:55:11 +0100, AngeloGioacchino Del Regno wrote:
> This series adds MTU3 nodes to the MT8188 base devicetree, fixes the
> Geralt Chromebooks to use it, and adds support for all of the USB
> ports, including TypeC Power Delivery, Alternate Modes, etc, found
> on the MediaTek Genio 510 and Genio 700 Evaluation Kits.
> 
> This also adds the missing SuperSpeed port to the mtk-xhci binding.
> 
> AngeloGioacchino Del Regno (3):
>   dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP
>   arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe
>     USB
>   arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX
> 
>  .../bindings/usb/mediatek,mtk-xhci.yaml       |   4 +
>  .../boot/dts/mediatek/mt8188-geralt.dtsi      |  18 +++
>  arch/arm64/boot/dts/mediatek/mt8188.dtsi      | 121 +++++++++-----
>  .../dts/mediatek/mt8390-genio-common.dtsi     | 151 +++++++++++++++++-
>  4 files changed, 251 insertions(+), 43 deletions(-)
> 
> --
> 2.48.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/mediatek/' for 20250220105514.43107-1-angelogioacchino.delregno@collabora.com:

arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dtb: rt1715@4e: 'vbus-supply' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/usb/richtek,rt1711h.yaml#
arch/arm64/boot/dts/mediatek/mt8370-genio-510-evk.dtb: jpeg-decoder@1a040000: iommus: [[137, 685], [137, 686], [137, 690], [137, 691], [137, 692], [137, 693]] is too long
	from schema $id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#
arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dtb: rt1715@4e: 'vbus-supply' does not match any of the regexes: 'pinctrl-[0-9]+'
	from schema $id: http://devicetree.org/schemas/usb/richtek,rt1711h.yaml#
arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dtb: jpeg-decoder@1a040000: iommus: [[139, 685], [139, 686], [139, 690], [139, 691], [139, 692], [139, 693]] is too long
	from schema $id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#

Re: [PATCH v3 0/3] MediaTek MT8188 MTU3 USB and Genio 510/700 TypeC

[Chunfeng Yun (云春峰)]

Hi Angelo
On Thu, 2025-02-20 at 11:55 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> This series adds MTU3 nodes to the MT8188 base devicetree, fixes the
> Geralt Chromebooks to use it, and adds support for all of the USB
> ports, including TypeC Power Delivery, Alternate Modes, etc, found
> on the MediaTek Genio 510 and Genio 700 Evaluation Kits.
> 
> This also adds the missing SuperSpeed port to the mtk-xhci binding.
> 
> AngeloGioacchino Del Regno (3):
>   dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP
>   arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe
>     USB
>   arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller,
> MUX
> 
>  .../bindings/usb/mediatek,mtk-xhci.yaml       |   4 +
>  .../boot/dts/mediatek/mt8188-geralt.dtsi      |  18 +++
>  arch/arm64/boot/dts/mediatek/mt8188.dtsi      | 121 +++++++++-----
>  .../dts/mediatek/mt8390-genio-common.dtsi     | 151
> +++++++++++++++++-
>  4 files changed, 251 insertions(+), 43 deletions(-)
Do these patch have also changed the chromebook's dts?

if changed it, do test it on chromebook?

Thanks


> 
> --
> 2.48.1
> 

Re: [PATCH v3 0/3] MediaTek MT8188 MTU3 USB and Genio 510/700 TypeC

[AngeloGioacchino Del Regno]

Il 22/02/25 09:45, Chunfeng Yun (云春峰) ha scritto:
> Hi Angelo
> On Thu, 2025-02-20 at 11:55 +0100, AngeloGioacchino Del Regno wrote:
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>
>>
>> This series adds MTU3 nodes to the MT8188 base devicetree, fixes the
>> Geralt Chromebooks to use it, and adds support for all of the USB
>> ports, including TypeC Power Delivery, Alternate Modes, etc, found
>> on the MediaTek Genio 510 and Genio 700 Evaluation Kits.
>>
>> This also adds the missing SuperSpeed port to the mtk-xhci binding.
>>
>> AngeloGioacchino Del Regno (3):
>>    dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP
>>    arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe
>>      USB
>>    arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller,
>> MUX
>>
>>   .../bindings/usb/mediatek,mtk-xhci.yaml       |   4 +
>>   .../boot/dts/mediatek/mt8188-geralt.dtsi      |  18 +++
>>   arch/arm64/boot/dts/mediatek/mt8188.dtsi      | 121 +++++++++-----
>>   .../dts/mediatek/mt8390-genio-common.dtsi     | 151
>> +++++++++++++++++-
>>   4 files changed, 251 insertions(+), 43 deletions(-)
> Do these patch have also changed the chromebook's dts?

Yes

> 
> if changed it, do test it on chromebook?

Yes, and there's no need to hide the MTU3 hardware on Chromebooks,
as I already mentioned multiple times.

Just lock it to host mode and it's always fine :-)

Cheers,
Angelo

> 
> Thanks
> 
> 
>>
>> --
>> 2.48.1
>>

Re: [PATCH v3 2/3] arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe USB

[Chen-Yu Tsai]

On Thu, Feb 20, 2025 at 7:00 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> The MT8188 SoC has three USB controllers, and all of them are behind
> the MTU3 DRD controller.
>
> Add the missing MTU3 nodes, default disabled, for all USB controllers
> and move the related XHCI nodes to be children of their MTU3 DRD to
> correctly describe the SoC.
>
> In order to retain USB functionality on all of the MT8188 and MT8390
> boards, also move the vusb33 supply and enable the relevant MTU3 nodes
> with special attention to the MT8188 Geralt Chromebooks, where it was
> necessary to set the dr_mode of all MTU3 controllers to host to avoid
> interfering with the EC performing DRD on its own.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Tested-by: Chen-Yu Tsai <wenst@chromium.org> # on MT8188 Ciri

> ---
>  .../boot/dts/mediatek/mt8188-geralt.dtsi      |  18 +++
>  arch/arm64/boot/dts/mediatek/mt8188.dtsi      | 121 ++++++++++++------
>  .../dts/mediatek/mt8390-genio-common.dtsi     |  28 ++++
>  3 files changed, 125 insertions(+), 42 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
> index b6abecbcfa81..faed5c8bc721 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
> @@ -1103,6 +1103,12 @@ &u3phy2 {
>  };
>
>  /* USB detachable base */
> +&ssusb0 {
> +       dr_mode = "host";
> +       vusb33-supply = <&pp3300_s3>;
> +       status = "okay";
> +};
> +
>  &xhci0 {
>         /* controlled by EC */
>         vbus-supply = <&pp3300_z1>;
> @@ -1110,6 +1116,12 @@ &xhci0 {
>  };
>
>  /* USB3 hub */
> +&ssusb1 {
> +       dr_mode = "host";
> +       vusb33-supply = <&pp3300_s3>;
> +       status = "okay";
> +};
> +
>  &xhci1 {
>         vusb33-supply = <&pp3300_s3>;
>         vbus-supply = <&pp5000_usb_vbus>;
> @@ -1117,6 +1129,12 @@ &xhci1 {
>  };
>
>  /* USB BT */
> +&ssusb2 {
> +       dr_mode = "host";
> +       vusb33-supply = <&pp3300_s3>;
> +       status = "okay";
> +};
> +
>  &xhci2 {
>         /* no power supply since MT7921's power is controlled by PCIe */
>         /* MT7921's USB BT has issues with USB2 LPM */
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index d2e1ff7236b1..c226998b7e47 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -1649,6 +1649,38 @@ spi5: spi@11019000 {
>                         status = "disabled";
>                 };
>
> +               ssusb1: usb@11201000 {
> +                       compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
> +                       reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
> +                       reg-names = "mac", "ippc";
> +                       ranges = <0 0 0 0x11200000 0 0x3f00>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       assigned-clocks = <&topckgen CLK_TOP_USB_TOP>;
> +                       assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +                       clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
> +                                <&topckgen CLK_TOP_SSUSB_TOP_REF>,
> +                                <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
> +                       clock-names = "sys_ck", "ref_ck", "mcu_ck";
> +                       phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
> +                       wakeup-source;
> +                       mediatek,syscon-wakeup = <&pericfg 0x468 2>;
> +                       status = "disabled";
> +
> +                       xhci1: usb@0 {
> +                               compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
> +                               reg = <0 0 0 0x1000>;
> +                               reg-names = "mac";
> +                               interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
> +                               assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>;
> +                               assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +                               clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
> +                               clock-names = "sys_ck";
> +                               status = "disabled";
> +                       };
> +               };
> +
>                 eth: ethernet@11021000 {
>                         compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",
>                                      "snps,dwmac-5.10a";
> @@ -1746,27 +1778,6 @@ queue3 {
>                         };
>                 };
>
> -               xhci1: usb@11200000 {
> -                       compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
> -                       reg = <0 0x11200000 0 0x1000>,
> -                             <0 0x11203e00 0 0x0100>;
> -                       reg-names = "mac", "ippc";
> -                       interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
> -                       phys = <&u2port1 PHY_TYPE_USB2>,
> -                              <&u3port1 PHY_TYPE_USB3>;
> -                       assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
> -                                         <&topckgen CLK_TOP_SSUSB_XHCI>;
> -                       assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> -                                                <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> -                       clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
> -                                <&topckgen CLK_TOP_SSUSB_TOP_REF>,
> -                                <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
> -                       clock-names = "sys_ck", "ref_ck", "mcu_ck";
> -                       mediatek,syscon-wakeup = <&pericfg 0x468 2>;
> -                       wakeup-source;
> -                       status = "disabled";
> -               };
> -
>                 mmc0: mmc@11230000 {
>                         compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
>                         reg = <0 0x11230000 0 0x10000>,
> @@ -1867,42 +1878,68 @@ imp_iic_wrap_c: clock-controller@11283000 {
>                         #clock-cells = <1>;
>                 };
>
> -               xhci2: usb@112a0000 {
> -                       compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
> -                       reg = <0 0x112a0000 0 0x1000>,
> -                             <0 0x112a3e00 0 0x0100>;
> +               ssusb2: usb@112a1000 {
> +                       compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
> +                       reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
>                         reg-names = "mac", "ippc";
> -                       interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
> -                       phys = <&u2port2 PHY_TYPE_USB2>;
> -                       assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
> -                                         <&topckgen CLK_TOP_USB_TOP_3P>;
> -                       assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> -                                                <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +                       ranges = <0 0 0 0x112a0000 0 0x3f00>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
> +                       assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
>                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
>                                  <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>,
>                                  <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
>                         clock-names = "sys_ck", "ref_ck", "mcu_ck";
> +                       phys = <&u2port2 PHY_TYPE_USB2>;
> +                       wakeup-source;
> +                       mediatek,syscon-wakeup = <&pericfg 0x470 2>;
>                         status = "disabled";
> +
> +                       xhci2: usb@0 {
> +                               compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
> +                               reg = <0 0 0 0x1000>;
> +                               reg-names = "mac";
> +                               interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
> +                               assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
> +                               assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +                               clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
> +                               clock-names = "sys_ck";
> +                               status = "disabled";
> +                       };
>                 };
>
> -               xhci0: usb@112b0000 {
> -                       compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
> -                       reg = <0 0x112b0000 0 0x1000>,
> -                             <0 0x112b3e00 0 0x0100>;
> +               ssusb0: usb@112b1000 {
> +                       compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
> +                       reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
>                         reg-names = "mac", "ippc";
> -                       interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
> -                       phys = <&u2port0 PHY_TYPE_USB2>;
> -                       assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
> -                                         <&topckgen CLK_TOP_USB_TOP_2P>;
> -                       assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> -                                                <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +                       ranges = <0 0 0 0x112b0000 0 0x3f00>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
> +                       assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
>                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
>                                  <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>,
>                                  <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
>                         clock-names = "sys_ck", "ref_ck", "mcu_ck";
> -                       mediatek,syscon-wakeup = <&pericfg 0x460 2>;
> +                       phys = <&u2port0 PHY_TYPE_USB2>;
>                         wakeup-source;
> +                       mediatek,syscon-wakeup = <&pericfg 0x460 2>;
>                         status = "disabled";
> +
> +                       xhci0: usb@0 {
> +                               compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
> +                               reg = <0 0 0 0x1000>;
> +                               reg-names = "mac";
> +                               interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
> +                               assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
> +                               assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +                               clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
> +                               clock-names = "sys_ck";
> +                               status = "disabled";
> +                       };
>                 };
>
>                 pcie: pcie@112f0000 {
> diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> index a37cf102a6e9..fd977daa4185 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> @@ -1011,13 +1011,25 @@ &u3phy2 {
>         status = "okay";
>  };
>
> +&ssusb0 {
> +       dr_mode = "host";
> +       vusb33-supply = <&mt6359_vusb_ldo_reg>;
> +       status = "okay";
> +};
> +
>  &xhci0 {
>         status = "okay";
> +};
> +
> +&ssusb1 {
> +       dr_mode = "host";
>         vusb33-supply = <&mt6359_vusb_ldo_reg>;
> +       status = "okay";
>  };
>
>  &xhci1 {
>         status = "okay";
> +       vdd-supply = <&usb_hub_fixed_3v3>;
>         vusb33-supply = <&mt6359_vusb_ldo_reg>;
>         #address-cells = <1>;
>         #size-cells = <0>;
> @@ -1037,6 +1049,22 @@ hub_3_0: hub@2 {
>                 reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
>                 vdd-supply = <&usb_hub_fixed_3v3>;
>         };
> +
> +       port {
> +               xhci_ss_ep: endpoint {
> +                       remote-endpoint = <&typec_con_ss>;
> +               };
> +       };
> +};
> +
> +&ssusb2 {
> +       interrupts-extended = <&gic GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>,
> +                             <&pio 220 IRQ_TYPE_LEVEL_HIGH>;
> +       interrupt-names = "host", "wakeup";
> +
> +       dr_mode = "host";
> +       vusb33-supply = <&mt6359_vusb_ldo_reg>;
> +       status = "okay";
>  };
>
>  &xhci2 {
> --
> 2.48.1
>
>

Re: [PATCH v3 1/3] dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP

[AngeloGioacchino Del Regno]

Il 20/02/25 18:18, Conor Dooley ha scritto:
> On Thu, Feb 20, 2025 at 11:55:12AM +0100, AngeloGioacchino Del Regno wrote:
>> Add a port used to connect the SuperSpeed output endpoint to a
>> Type-C connector.
>>
>> Note that the MediaTek XHCI controllers are always in front of a
>> different controller handling the USB HS (usually, MTU3), so the
>> only port that this controller provides is SuperSpeed, while the
>> HighSpeed one comes from elsewhere.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Is everyone okay if I pick this (and the MTU3 one [1]) in the MediaTek trees?

This is so that I don't get devicetree warnings when picking the DT patches
that are adding USB MUX/TCPC to the MediaTek boards.

[1] 
https://lore.kernel.org/all/0e58bfb8f2f7b7e83e3da6075986ddbcc84531fc.camel@mediatek.com

Thanks,
Angelo

Re: [PATCH v3 0/3] MediaTek MT8188 MTU3 USB and Genio 510/700 TypeC

[AngeloGioacchino Del Regno]

On Thu, 20 Feb 2025 11:55:11 +0100, AngeloGioacchino Del Regno wrote:
> This series adds MTU3 nodes to the MT8188 base devicetree, fixes the
> Geralt Chromebooks to use it, and adds support for all of the USB
> ports, including TypeC Power Delivery, Alternate Modes, etc, found
> on the MediaTek Genio 510 and Genio 700 Evaluation Kits.
> 
> This also adds the missing SuperSpeed port to the mtk-xhci binding.
> 
> [...]

Applied to v6.14-next/dts64, thanks!

[1/3] dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP
      commit: 454a1e3cd36c113341d7b71e8e691c6e47ab4a8a
[2/3] arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe USB
      commit: 598c4ad870d3942ea948d2b99c55239acdde3224
[3/3] arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX
      commit: 1afaeca17238ef6480b1a76e7fd8b3c33d406ef7

Cheers,
Angelo