Re: [PATCH] usb: dwc3: Use the correct PHY mode for USB3 PHY

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] usb: dwc3: Missing PHY_MODE_USB_DEVICE_SS for USB3 PHYs device mode
- [High] usb: dwc3: Unconditional PHY_MODE_USB_HOST_SS breaks existing PHY drivers
--

commit 0fa2a51031f656c2f62abc5514732f044e86b041
Author: Prashanth K <prashanth.k@oss.qualcomm.com>

usb: dwc3: Use the correct PHY mode for USB3 PHY

This commit configures USB3 PHYs with PHY_MODE_USB_HOST_SS instead of
PHY_MODE_USB_HOST when switching the controller to host mode. It is intended
to accommodate PHY drivers that distinguish between USB2 and SS host modes.

> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -251,7 +251,7 @@ static void __dwc3_set_mode(struct work_struct *work)
>  			for (i = 0; i < dwc->num_usb2_ports; i++)
>  				phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
>  			for (i = 0; i < dwc->num_usb3_ports; i++)
> -				phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> +				phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST_SS);

[Severity: High]
Does this change break host mode switching for PHY drivers that only support
PHY_MODE_USB_HOST?

Unlike the USB core in drivers/usb/core/hcd.c which attempts to fall back
to PHY_MODE_USB_HOST if PHY_MODE_USB_HOST_SS is rejected, the DWC3 core
ignores the return value from phy_set_mode() and has no fallback mechanism.

Many existing DWC3-compatible USB3 PHY drivers, such as the MediaTek TPHY
(phy-mtk-tphy.c and phy-mtk-xsphy.c), only handle PHY_MODE_USB_HOST. When
passed PHY_MODE_USB_HOST_SS, their mode switch statements fall into the
default branch and do nothing. This leaves the PHY registers like
P2C_FORCE_IDDIG un-updated for host operation, which silently breaks DRD
host mode switching for these platforms.

[ ... ]

> @@ -1643,7 +1643,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
>  		for (i = 0; i < dwc->num_usb2_ports; i++)
>  			phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
>  		for (i = 0; i < dwc->num_usb3_ports; i++)
> -			phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> +			phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST_SS);

[Severity: High]
By updating the host mode path to use PHY_MODE_USB_HOST_SS, does the
peripheral mode path also need to be updated to use PHY_MODE_USB_DEVICE_SS
for USB3 PHYs?

Currently, in __dwc3_set_mode() and dwc3_core_init_mode(), dwc3 continues
to unconditionally pass PHY_MODE_USB_DEVICE to usb3_generic_phy during
peripheral configuration:

__dwc3_set_mode() {
        ...
        case DWC3_GCTL_PRTCAP_DEVICE:
                ...
                phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
        ...
}

Modern USB3 PHY drivers, such as the Qualcomm QMP PHY (phy-qcom-qmp-usb.c),
explicitly check for qmp->mode == PHY_MODE_USB_DEVICE_SS to configure
SuperSpeed-specific interrupt masks like ALFPS_DTCT_EN for LFPS detection.

Because dwc3 passes PHY_MODE_USB_DEVICE, the QMP PHY drivers fall back to
the legacy USB2 interrupt mask. This breaks SuperSpeed wake/resume
functionality from autonomous or suspend modes when the DWC3 controller
operates as a gadget.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012093704.2762263-1-prashanth.k@oss.qualcomm.com?part=1