From: sashiko-bot@kernel.org
To: "Peter Chen" <peter.chen@oss.qualcomm.com>
Cc: linux-usb@vger.kernel.org
Subject: Re: [PATCH 1/1] arm64: dts: qcom: glymur: Set snps,resume-hs-terminations for USB controllers
Date: Fri, 16 Oct 2026 09:23:56 +0000 [thread overview]
Message-ID: <sashiko-outbox-174076@kernel.org> (raw)
In-Reply-To: <20261016091336.2715717-1-peter.chen@oss.qualcomm.com>
> The DWC3 controllers on Glymur are paired with the M31 eUSB2 PHY.
> According to HPG, host-mode USB2 L2/L1 resume with this PHY, GUCTL1[10]
> (RESUME_OPMODE_HS_HOST) must be set.
>
> Without this bit setting, USB2 HS device cannot be reset after it is
> runtime resumed. For example, after:
>
> echo on > /sys/bus/usb/devices/1-1/power/control
>
> PORTSC.PR never clears (PORTSC = 0xe11) and the hub driver fails with
> "port_wait_reset: err = -16".
>
> Set snps,resume-hs-terminations on all Glymur USB controllers. This
> makes dwc3 core set GUCTL1[10] and fixes the issue, tested on Glymur CRD.
>
> Fixes: 4eee57dd4df9 ("arm64: dts: qcom: glymur: Add USB related nodes")
> Assisted-by: Claude:claude-opus-5-5
> Signed-off-by: Peter Chen <peter.chen@oss.qualcomm.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261016091336.2715717-1-peter.chen@oss.qualcomm.com?part=1
next prev parent reply other threads:[~2026-10-16 9:23 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 9:13 [PATCH 1/1] arm64: dts: qcom: glymur: Set snps,resume-hs-terminations for USB controllers Peter Chen
2026-10-16 9:23 ` sashiko-bot [this message]
2026-10-16 9:24 ` Konrad Dybcio
2026-10-16 9:31 ` Peter Chen
2026-10-16 10:24 ` Konrad Dybcio
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