Re: [PATCH] watchdog: renesas_wdt: Fix interrupt enable for timer

["\"グェン・アン・ホァン\"" <na-hoan@jinso.co.jp>]

Dear Wolfram-san
Dear Geert- san

Thank you very much
Wolfram Sang wrote:
> Hi,
> 
> On Thu, May 23, 2019 at 06:29:37PM +0900, Nguyen An Hoan wrote:
> > From: Hoan Nguyen An <na-hoan@jinso.co.jp>
> > 
> > Fix setting for bit WOVFE of RWTCSRA. Keep it enable follow hardware document.
> 
> Hmm, I can't find it in the docs. Which version of the documentation do
> you use?
> 
> 
> > -	rwdt_write(priv, priv->cks, RWTCSRA);
> > +	val |= priv->cks;
> > +	rwdt_write(priv, val, RWTCSRA);
> 
> Have you tested this successfully? According to the docs, CKS bits are
> all 1 by default. So, your |= operation should be a NOP and we can't
> select a CKS value anymore if I am not mistaken.
> 
I tested and can confirm WOVFE was be disable by command 
rwdt_write(priv, priv->cks, RWTCSRA);
I don't understand why this bit is turned off but the watchdog can still reset, but 
according to the document it will be 1.

> >  	rwdt_write(priv, 0, RWTCSRB);
> >  
> >  	while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
> >  		cpu_relax();
> > -
> > -	rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
> > +	/* Enable interrupt and timer */
> > +	rwdt_write(priv, val | RWTCSRA_WOVFE | RWTCSRA_TME, RWTCSRA);
> 
> What is the use of enabling an interrupt without having an interrupt
> handler? (And I never understood why there is an interrupt for an
> overflowing watchdog. We won't have time to serve it, or am I
> overlooking something obvious?)

I have added the interrupt node to dtsi and created the interrupt handler to successfully handle the Secure watchdog Gen2, but this is not documented.  With Gen 3, I am also thinking whether it is necessary or not.  Thank you!!!
With Gen3, after reset by WDT, then restart will have an interrupt when probe timer(), but we can do this no reset, after this,  timer operate normally. 
Problaly this patch should RFC

Thank you for your helps!!!


> 
> Kind regards,
> 
>    Wolfram
>