Re: [PATCH 1/4] clocksource/drivers/timer-tegra186: Fix support for multiple watchdog instances

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The read-modify-write sequence on the shared TKEIE register lacks synchronization, causing a data race when multiple watchdogs are enabled concurrently.
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commit b62fcb75a56d43aa9fdaf906df5a4e961258346d
Author: Kartik Rajput <kkartik@nvidia.com>

clocksource/drivers/timer-tegra186: Fix support for multiple watchdog instances

This commit fixes support for multiple watchdog instances on Tegra186 by
changing the interrupt enable register update to a read-modify-write sequence.
This preserves the interrupt enable bits for previously configured watchdogs.

> diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c
> index 355558893e5f3..bfe16d2d5104e 100644
> --- a/drivers/clocksource/timer-tegra186.c
> +++ b/drivers/clocksource/timer-tegra186.c
> @@ -149,7 +149,8 @@ static void tegra186_wdt_enable(struct tegra186_wdt *wdt)
>  	u32 value;
>  
>  	/* unmask hardware IRQ, this may have been lost across powergate */
> -	value = TKEIE_WDT_MASK(wdt->index, 1);
> +	value = readl(tegra->regs + TKEIE(wdt->tmr->hwirq));
> +	value |= TKEIE_WDT_MASK(wdt->index, 1);
> +	writel(value, tegra->regs + TKEIE(wdt->tmr->hwirq));

Does this read-modify-write sequence need synchronization?

All watchdogs share the same TKEIE register since wdt->tmr->hwirq is
hardcoded to 0. Operations across different watchdog devices are not
serialized by the watchdog core, which only uses a per-device mutex.

If a userspace watchdog is started concurrently while a kernel watchdog is
being enabled, the read-modify-write sequences can overlap. If this happens,
one watchdog's interrupt enable bit can be silently overwritten and cleared.

Without its interrupt, the kernel watchdog could fail to ping itself,
resulting in an unintended system POR reset.

Could this shared MMIO register update be protected with a driver-level
spinlock in struct tegra186_timer?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260507154557.2082697-1-kkartik@nvidia.com?part=1