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([81.56.18.151]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4995c7b2b68sm209832495e9.4.2026.08.09.09.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Aug 2026 09:07:14 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 5/8] dt-bindings: reset: Add reset controller constants for mt8167 Date: Sun, 9 Aug 2026 18:03:29 +0200 Message-ID: <20260809160643.33991-6-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260809160643.33991-1-l.scorcia@gmail.com> References: <20260809160643.33991-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the various bits that identify watchdog and mmsys resets. IDs for mmsys resets restart from zero as they are used in a different device. Signed-off-by: Luca Leonardo Scorcia --- .../reset/mediatek,mt8167-resets.h | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt8167-resets.h diff --git a/include/dt-bindings/reset/mediatek,mt8167-resets.h b/include/dt-bindings/reset/mediatek,mt8167-resets.h new file mode 100644 index 000000000000..af8a3e499f8b --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt8167-resets.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8167 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8167 + +/* TOPRGU resets, these are actual bits in the register */ +#define MT8167_TOPRGU_DDRPHY_FLASH_RST 0 +#define MT8167_TOPRGU_AUD_PAD_RST 1 +#define MT8167_TOPRGU_MM_RST 2 +#define MT8167_TOPRGU_MFG_RST 3 +#define MT8167_TOPRGU_MDSYS_RST 4 +#define MT8167_TOPRGU_CONN_RST 5 +#define MT8167_TOPRGU_PAD2CAM_DIG_MIPI_RX_RST 6 +#define MT8167_TOPRGU_DIG_MIPI_TX_RST 7 +#define MT8167_TOPRGU_SPI_PAD_MACRO_RST 8 +/* The data sheet describes bit 9 as "reserved, unused" */ +#define MT8167_TOPRGU_APMIXED_RST 10 +#define MT8167_TOPRGU_VDEC_RST 11 +#define MT8167_TOPRGU_CONN_MCU_RST 12 +#define MT8167_TOPRGU_EFUSE_RST 13 +#define MT8167_TOPRGU_PWRAP_SPICTL_RST 14 +#define MT8167_TOPRGU_SW_RST_NUM 15 + +/* MMSYS resets, these are IDs */ +#define MT8167_MMSYS_SW0_RST_B_SMI_COMMON 0 +#define MT8167_MMSYS_SW0_RST_B_SMI_LARB0 1 +#define MT8167_MMSYS_SW0_RST_B_CAM_MDP 2 +#define MT8167_MMSYS_SW0_RST_B_MDP_RDMA0 3 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ0 4 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ1 5 +#define MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0 6 +#define MT8167_MMSYS_SW0_RST_B_MDP_WDMA 7 +#define MT8167_MMSYS_SW0_RST_B_MDP_WROT0 8 +#define MT8167_MMSYS_SW0_RST_B_FAKE_ENG 9 +#define MT8167_MMSYS_SW0_RST_B_MUTEX 10 +#define MT8167_MMSYS_SW0_RST_B_DISP_OVL0 11 +#define MT8167_MMSYS_SW0_RST_B_DISP_RDMA0 12 +#define MT8167_MMSYS_SW0_RST_B_DISP_RDMA1 13 +#define MT8167_MMSYS_SW0_RST_B_DISP_WDMA0 14 +#define MT8167_MMSYS_SW0_RST_B_DISP_COLOR 15 +#define MT8167_MMSYS_SW0_RST_B_DISP_CCORR 16 +#define MT8167_MMSYS_SW0_RST_B_DISP_AAL 17 +#define MT8167_MMSYS_SW0_RST_B_DISP_GAMMA 18 +#define MT8167_MMSYS_SW0_RST_B_DISP_DITHER 19 +#define MT8167_MMSYS_SW0_RST_B_DISP_UFOE 20 +#define MT8167_MMSYS_SW0_RST_B_DISP_PWM 21 +#define MT8167_MMSYS_SW0_RST_B_DSI0 22 +#define MT8167_MMSYS_SW0_RST_B_DPI0 23 +#define MT8167_MMSYS_SW0_RST_B_MIPI_TX_CONFIG 24 +#define MT8167_MMSYS_SW1_RST_B_LVDS_ENCODER 25 +#define MT8167_MMSYS_SW1_RST_B_DPI1 26 +#define MT8167_MMSYS_SW1_RST_B_HDMI 27 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8167 */ -- 2.43.0