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([81.56.18.151]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4995c7b2b68sm209832495e9.4.2026.08.09.09.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Aug 2026 09:07:21 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 8/8] soc: mediatek: mtk-mmsys: Add resets for mt8167 Date: Sun, 9 Aug 2026 18:03:32 +0200 Message-ID: <20260809160643.33991-9-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260809160643.33991-1-l.scorcia@gmail.com> References: <20260809160643.33991-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The mt8167 SoC has 64 MMSYS resets, split in two contiguous 32-bits registers, MMSYS_SW0_RST_B (0x140) and MMSYS_SW1_RST_B (0x144), as also stated in the downstream kernel for the Lenovo Smart Clock in the ddp_reg.h header. Signed-off-by: Luca Leonardo Scorcia --- drivers/soc/mediatek/mt8167-mmsys.h | 3 +++ drivers/soc/mediatek/mtk-mmsys.c | 38 +++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h index eef14083c47b..27793462ce0d 100644 --- a/drivers/soc/mediatek/mt8167-mmsys.h +++ b/drivers/soc/mediatek/mt8167-mmsys.h @@ -3,6 +3,9 @@ #ifndef __SOC_MEDIATEK_MT8167_MMSYS_H #define __SOC_MEDIATEK_MT8167_MMSYS_H +#define MT8167_MMSYS_SW0_RST_B 0x140 +#define MT8167_MMSYS_SW1_RST_B 0x144 + #define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030 #define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038 #define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x058 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 2f3e0778bb17..02649225e8a7 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -4,6 +4,7 @@ * Author: James Liao */ +#include #include #include #include @@ -53,10 +54,47 @@ static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", }; +static const u8 mmsys_mt8167_rst_tb[] = { + [MT8167_MMSYS_SW0_RST_B_SMI_COMMON] = MMSYS_RST_NR(0, 0), + [MT8167_MMSYS_SW0_RST_B_SMI_LARB0] = MMSYS_RST_NR(0, 1), + [MT8167_MMSYS_SW0_RST_B_CAM_MDP] = MMSYS_RST_NR(0, 2), + [MT8167_MMSYS_SW0_RST_B_MDP_RDMA0] = MMSYS_RST_NR(0, 3), + [MT8167_MMSYS_SW0_RST_B_MDP_RSZ0] = MMSYS_RST_NR(0, 4), + [MT8167_MMSYS_SW0_RST_B_MDP_RSZ1] = MMSYS_RST_NR(0, 5), + [MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0] = MMSYS_RST_NR(0, 6), + [MT8167_MMSYS_SW0_RST_B_MDP_WDMA] = MMSYS_RST_NR(0, 7), + [MT8167_MMSYS_SW0_RST_B_MDP_WROT0] = MMSYS_RST_NR(0, 8), + [MT8167_MMSYS_SW0_RST_B_FAKE_ENG] = MMSYS_RST_NR(0, 9), + [MT8167_MMSYS_SW0_RST_B_MUTEX] = MMSYS_RST_NR(0, 10), + [MT8167_MMSYS_SW0_RST_B_DISP_OVL0] = MMSYS_RST_NR(0, 11), + [MT8167_MMSYS_SW0_RST_B_DISP_RDMA0] = MMSYS_RST_NR(0, 12), + [MT8167_MMSYS_SW0_RST_B_DISP_RDMA1] = MMSYS_RST_NR(0, 13), + [MT8167_MMSYS_SW0_RST_B_DISP_WDMA0] = MMSYS_RST_NR(0, 14), + [MT8167_MMSYS_SW0_RST_B_DISP_COLOR] = MMSYS_RST_NR(0, 15), + [MT8167_MMSYS_SW0_RST_B_DISP_CCORR] = MMSYS_RST_NR(0, 16), + [MT8167_MMSYS_SW0_RST_B_DISP_AAL] = MMSYS_RST_NR(0, 17), + [MT8167_MMSYS_SW0_RST_B_DISP_GAMMA] = MMSYS_RST_NR(0, 18), + [MT8167_MMSYS_SW0_RST_B_DISP_DITHER] = MMSYS_RST_NR(0, 19), + [MT8167_MMSYS_SW0_RST_B_DISP_UFOE] = MMSYS_RST_NR(0, 20), + [MT8167_MMSYS_SW0_RST_B_DISP_PWM] = MMSYS_RST_NR(0, 21), + [MT8167_MMSYS_SW0_RST_B_DSI0] = MMSYS_RST_NR(0, 22), + [MT8167_MMSYS_SW0_RST_B_DPI0] = MMSYS_RST_NR(0, 23), + /* bit 24 is SMI_COMMON again according to data sheet */ + /* bit 25 is SMI_LARB0 again according to data sheet */ + [MT8167_MMSYS_SW0_RST_B_MIPI_TX_CONFIG] = MMSYS_RST_NR(0, 26), + /* all other bits are not described in data sheet */ + [MT8167_MMSYS_SW1_RST_B_LVDS_ENCODER] = MMSYS_RST_NR(1, 2), + [MT8167_MMSYS_SW1_RST_B_DPI1] = MMSYS_RST_NR(1, 3), + [MT8167_MMSYS_SW1_RST_B_HDMI] = MMSYS_RST_NR(1, 4), +}; + static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .clk_driver = "clk-mt8167-mm", .routes = mt8167_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), + .sw0_rst_offset = MT8167_MMSYS_SW0_RST_B, + .rst_tb = mmsys_mt8167_rst_tb, + .num_resets = ARRAY_SIZE(mmsys_mt8167_rst_tb), }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { -- 2.43.0